Multi-threaded processing architecture to accelerate physical sign-off for its IC Validator tool. Nick Flaherty reports
The challenge of system-on-chip devices with billions of transistors have given design tool developers a major headache.
Validating and checking these massive designs can take days, slowing down the development cycle.
Synopsys has used a massively parallel multi-threaded processing architecture to accelerate physical sign-off for its IC Validator tool.
Using distributed processing and efficient resource management, IC Validator has enabled physical sign-off within hours on designs with 10 billion+ transistors while reducing the memory and disk usage requirements by half.
This enables the tool to use several hundreds of CPUs by taking advantage of the smaller and more readily available machines in the customers' existing compute farms.
"Increasing manufacturing complexity at advanced nodes makes it challenging for customers to complete physical sign-off within schedule," said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. "Through high-performance scalability and readily available, optimised runsets from all major foundries, IC Validator is providing our customers with the fastest path to production silicon."
IC Validator, part of the Synopsys Digital Design Platform, includes design rule checking (DRC), programmable electrical rule checks (ERC), dummy fill and design-for-manufacturing (DFM) enhancement.
Up to 8 CPUs can be used with a single license, and more with additional licenses, and uses both multi-threading and distributed processing over multiple machines.
This enables coding at higher levels of abstraction and is architected for mainstream hardware, using smart memory-aware load scheduling and balancing technologies.