The Safety Enhancement Package (SEP) for Synopsys' DesignWare ARC EM processors that include cache support and DSP acceleration. The ARC EM4, EM6, EM5D and EM7D cores, combined with the ARC SEP option, have been certified ASIL D Ready by SGS-TÜV Saar, a leading independent certification company.
The ultra-compact cores incorporate critical safety features such as Error-Correcting Code (ECC) and a programmable watchdog timer for detecting system failures. The SEP option adds a lockstep interface and comprehensive safety documentation that facilitate chip- and system-level ISO 26262 ASIL D compliance. In addition, software developers can accelerate the development of ISO 26262-compliant code with the ASIL D Ready certified ARC MetaWare Compiler. The ARC EM cores with SEP are designed to meet the small area and rigorous safety requirements of system-on-chips (SoCs) targeting a broad range of automotive applications including sensors, controllers and advanced driver assistance systems (ADAS).
"The increasing number of electronic systems being used for safety-critical functions in vehicles requires stringent safety standards to help prevent catastrophic failures in these systems," said Wolfgang Ruf, product manager, semiconductors at SGS-TÜV Saar. "By achieving ASIL D Ready certification for its DesignWare ARC EM processors, Synopsys is enabling automotive system designers to achieve ISO 26262 certification faster and with less effort."
All ARC EM processors are configurable and extensible to meet the unique performance, power and area requirements of each target application. ARC processors have been successfully deployed in automotive applications for years, and in 2013 Synopsys introduced the Safety Enhancement Package for ARC EM4 cores to help automotive chip designers meet the specific requirements of the ISO 26262 functional safety standard.
To address the evolving processing requirements in automotive applications such as motor control and sensor fusion, the SEP option is being extended to EM processors that support DSP functions and incorporate up to 32 Kbytes of instruction and data caches. In addition, the EM cores with the SEP option are the first cores in their class to be certified ASIL D Ready. The combination of the ARC EM cores' integrated hardware safety features, ASIL certification and safety-related collateral such as a Failure Modes, Effects, and Diagnostic Analysis (FMEDA) report saves a utomotive designers months of effort in their SoC development and ISO 26262 certification process.
The DesignWare ARC MetaWare Development Toolkit for Safety is a complete solution for developing, debugging and optimizing embedded software targeted for ARC processors. Included in the toolkit is an ASIL D Ready certified compiler and safety collateral, including a safety manual and safety guide, to help developers of safety-critical systems fulfill the requirements of the ISO 26262 standard and prepare for compliance testing.
"The use of embedded processors in automobiles is growing rapidly, and achieving functional safety certification of these processor-based systems is essential for automotive designers," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "By providing an extensive portfolio of ASIL Ready DesignWare IP, including the silicon-proven ARC EM processors with SEP option and software development tools, Synopsys helps designers accelerate the development and qualification of automotive SoCs."
The ASIL D Ready certified DesignWare ARC EM4, EM6, EM5D and EM7D cores with SEP package, and the MetaWare Toolkit for Safety are available now.