Cadence Design Systems has launched the latest version of its signal analysis design tool with several key features specifically designed to speed up PCB power and signal integrity sign-off.
Sigrity 2017 includes an Allegro PowerTree topology viewer and editor, which enable designers to quickly assess power delivery decisions early in the design cycle, as well as a PCI Express (PCIe) 4.0 compliance kit for checking signal integrity compliance with the latest PCIe specification when it is certified later this year.
The ability to accelerate PCB power and signal integrity signoff is not only critical for designing standalone circuit boards, but is also an important element for designing complete end products. Sigrity 2017 is one of Cadence’s System Design Enablement technologies helping companies to create innovative, high-quality electronic products from chips, to boards and entire systems.
Determining the path for power delivery early in the design cycle is critical to PCB design teams.
The PowerTree user interface allows for a power topology to be viewed for quick and accurate determination of the best path for power delivery. The technology also allows for easy editing as designs change.
The information stored in the PowerTree environment is then used later in the design cycle to provide automated setup of post-route power integrity analysis for faster closure.
Also included in the Sigrity 2017 release is library management for power integrity models through the analysis model manager.
Models can be saved and automatically retrieved from the analysis model manager library when design components are reused. This method also speeds development by automating processes that in the past have been repeatedly carried out manually.
For PCIe 4.0 designs the Sigrity SystemSI Serial Link Analysis tool automatically qualifies signal quality standards instead of manually checking and measuring against standards documents.
“The Sigrity 2017 portfolio includes technology designed to increase efficiency and speed up the design process,” said Steve Durrill, Senior Product Engineering Group Director at Cadence. “Each of the features we’ve updated have been improved with the goal of helping our customers get high-performing products out the door faster. The work we’ve done to develop the PCIe 4.0 compliance kit even before the standard has been ratified is a visible and important example of this focus on customer requirements and time to market.”