Vicor Corporation announces the introduction of Power-on-Package modular current multipliers for high performance, high current, CPU/GPU/ASIC (XPU) processors.
By freeing up XPU socket pins and eliminating losses associated with delivery of current from the motherboard to the XPU, Vicor’s Power-on-Package solution enables higher current delivery for maximum XPU performance.
In response to the ever-increasing demands of high performance applications – artificial intelligence, machine learning, big data mining – XPU operating currents have risen to hundreds of Amperes.
Point-of-Load power architectures in which high current power delivery units are placed close to the XPU mitigate power distribution losses on the motherboard but do nothing to lessen interconnect challenges between the XPU and the motherboard.
With increasing XPU currents, the remaining short distance to the XPU – the ‘last inch’ – consisting of motherboard conductors and interconnects within the XPU socket has become a limiting factor in XPU performance and total system efficiency.
Vicor’s new Power-on-Package Modular Current Multipliers (MCMs) fit within the XPU package to expand upon the efficiency, density, and bandwidth advantages of Vicor’s Factorized Power Architecture, already established in 48V Direct-to-XPU motherboard applications by early adopters.
As current multipliers, MCMs mounted on the XPU substrate under the XPU package lid, or outside of it, are driven at a fraction (eg, 1/64th) of the XPU current from an external Modular Current Driver (MCD).
The MCD, located on the motherboard, drives MCMs and accurately regulates the XPU voltage with high bandwidth and low noise.
The solution profiled today, consisting of two MCMs and one MCD, enables delivery of up to 320A of continuous current to the XPU, with peak current capability of 640A.
With MCMs mounted directly to the XPU substrate, the XPU current delivered by the MCMs does not traverse the XPU socket.
And, because the MCD drives MCMs at a low current, power from the MCD can be efficiently routed to MCMs reducing interconnect losses by 10x even though 90% of the XPU pins typically required for power delivery are reclaimed for expanded I/O functionality.
Additional benefits include a simplified motherboard design and a substantial reduction in the minimum bypass capacitance required to keep the XPU within its voltage limits.