Over the past five years, there has been an explosion of growth in the portable electronic industry with consequent opportunities for manufacturers of radio frequency (RF) components.
Today, the designers of compact electronic systems, especially handheld/wireless devices, are faced with tightening board space constraints, thus driving the requirement for alternative integrated passive technologies. For the portable handheld designer, success in the market comes from the ability to produce small handheld devices with long battery life in very high volumes. The handheld devices are attaining smaller practical size with miniaturisation coming from the reduction in size of components and their associated packages. Functional integration and miniaturisation is the key to this success!
To aid this miniaturisation campaign, a new generation of integrated components has emerged which offers the capability to integrate resistors, capacitors, inductors, diodes and transistors into a single monolithic device with minimal packaging overhead. By combining Thin-Film-on-Silicon wafer fabrication technology with an advanced DFN (Dual Flat No-Lead) and QFN (Quad Flat No-Lead) packaging process, component manufacturers such as Bourns Inc can now provide designers with an Integrated Passive and Active Device solution, which saves PCB real estate while at the same time offering remarkable electrical performance.
This article will discuss the Thin-film On Silicon technology used in the manufacturing of Integrated Passive and Active Devices in DFN and QFN packages. Typical functional applications including Line Filtering and ESD protection with associated performance characteristics are outlined.
Thin-Film passive components have been available to the electronic designer for many years. The Thin Film resistors are fabricated using a Tantalum Nitride (TaN) layer as the resistive material and an Aluminum metal layer for interconnect and contacting purposes. The Aluminum metal layer and Tantalum Nitride layers are uppermost in the resistor construction (except for the passivation layers) while the required resistor value is arrived at using the pattern geometry (R=rL/W) as the primary design parameter.
Thin film capacitors are normally fabricated using an Aluminum metal layer as the top electrode where the top Aluminum layer provides low parasitic resistance and inductance values for the interconnect. A Silicon Nitride layer is used as the dielectric and the carrier silicon substrate as the bottom electrode plate. The Thin Film capacitor value (C=µA/d) represents the surface area of the top metal plate area over a lower silicon plate with a dielectric material between the plates.
The Thin film inductor can be constructed in a Spiral or Square layout where the inductor value is a function of the outer diameter, inner diameter, and number of turns and thickness of the metal layer. Inductors are fabricated using the top Aluminum metal layer over a Tantalum Nitride (TaN) layer. A lower Aluminum metal layer provides the 'lead' into the inductor through a via hole. Thin Film resistors, capacitors and inductors are renowned for their stability, temperature characteristics and reliability. Typical
Thin-Film Resistor values are in the 10Ω–100kΩ range with ±10percent tolerances, Capacitor values in the range 20pF–300pF with ±20percent tolerances and Inductors of between 1nH–15nH also with ±20percent tolerances. These elements exhibit excellent performance over a broad frequency range.
Underneath the Thin-Film layers, the silicon substrate can be used to integrate diodes of various types (Schottky, Zener and Varactor) and bipolar transistors. These elements can be constructed on the silicon substrate using the material properties of the N or P silicon. With no board-level, copper-trace interconnections between these elements together with the most direct connection possible from component terminals to board pads, the behaviour of these devices is easily controlled and highly repeatable.
Another low cost small size package that is available is the DFN (Dual Flat No-lead) package, which is a plastic leadless chip carrier with dual (2 opposite) populated sides and exposed thermal pad and typical package height of 0.8mm. All surface mount contact pads have 100percent Sn terminations and 0.5mm contact pitch. This rectangular package conforms to JEDEC Package Outline MO-229 and provides 4, 6 and 8 I/O options. For easier PCB routing and higher density of contact pads, the QFN (Quad Flat No-lead) package offers a plastic leadless chip carrier with quad (4 opposite) populated sides and exposed thermal pad and typical package height of 0.75mm. All surface mount contact pads have RoHS Pb Free compliant 100percent Sn terminations and 0.5mm contact pitch. This square package conforms to JEDEC Package Outline MO-220 and provides 16 and 20 I/O options. For both package options, the singulated die is attached to the centre paddle lead frame and then wire bonded to the external I/O lead frames. The die and wire bonds are then over molded to achieve the nominal height of 0.75mm making them ideal for high volume SMT processing.
Cost consideration
Cost is a factor that will inevitably spring to mind in the context of Integrated Passive & Active Devices. After all, Thin-Film passive component technology has traditionally been associated with such applications as precision instrumentation, high accuracy converters and ultra-low-noise amplifiers. Here the reader may be surprised to learn that the installed cost of a well-designed Integrated Passive & Active Device can usually compare very favourably with the discrete solution that it is intended to replace. The term ‘installed cost’ is key here. When doing the math, it is very important to consider that the cost of installation does not end at the bill of materials. The main elements of the total installed cost include the price of the discrete components, the placement cost, cost of procurement and storage. The placement costs for discrete chip and/or SOT components are nearly always significantly higher than the cost of the components themselves. If this is borne in mind, as indeed it should be, the IPAD using DFN package becomes a very attractive proposition – especially when one considers the electrical and mechanical performance advantages already discussed. The costs in Table1 relate to the circuit in Fig.1.
From this example in Fig. 1 and Table 1, it is clear that there is a potential saving of nearly US$0.20 per part. Additional advantages include use of less solder paste and reduced number of solder joints. (45 for the discrete solution and 15 for the DFN solution) Furthermore the Integrated Passive & Active Devices are electrically tested during its manufacturing process whereas the discrete solution can only be tested once assembled on the PCB.
u ESD Protection: Many handheld devices have external ports, which are potential paths for ESD to enter the handheld device and damaging the internal circuitry. A very suitable solution for this type of problem, where board area is an issue, is Integrated Passive & Active Devices. Bourns provide ESD protection for contact discharge in excess of ±8KV and air discharges of ±15 KV. For this and most hand held devices the test method applicable is IEC 61000-4-2 specification.
u ESD Protection & EMI Filters: Handheld devices such as cell phones often have data and/or audio ports, which are used to connect the device to external devices such as laptop computers and headsets. Cell phones by their nature generate RF noise and this noise can be coupled into the data/audio port. Combing ESD Protection and a low pass filter will attenuate the RF noise, which may otherwise interfere with the internal base band circuitry of the cell phone. Typically, the Low Pass Filter it is used to protect data/audio ports on wireless devices and LCD screen interfaces. A typical schematic is shown in Fig. 2.
Summary
It is hoped that this article has shed some light on the capabilities of Thin-Film-on-Silicon Integrated Passive & Active Devices. In particular, the intent was to demonstrate how the advent of DFN (Dual Flat No-Lead) and QFN (Quad Flat No-Lead) packaging technology has made these versatile devices attractive to designers of miniature handheld products by eliminating any disadvantages attributable to previous packaging forms.
The integration of Resistors, Capacitors, Inductors, Diodes and Transistors into single, ultra-miniature, monolithic packages has opened the door to a new level of component count reduction. This allows the Bill of Materials to shrink, Pick and Place cycles to decrease and overall product manufacturing costs to come down. All with the advantages of reduced board real estate usage and improved electrical performance. u
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Ian Doyle is Product Line Manager with Bourns Electronics (Ireland), Cork, Ireland. www.bourns.com
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