ARC International and ARM have launched new processor architectures aimed at the video and automotive markets for the first time, taking on established players.
ARC has launched VRaptor, a combination of ARC750D cores with SIMD media co-processors and dedicated hardware accelerators, all linked by a new communications technology.
“VRaptor takes a holistic approach to SoC design by integrating configurable, scalable hardware and software with an optimised interconnect,” said Peter Hutton, senior vice president of engineering at ARC International.
For an SD resolution H.264 decoder, one 750D core would be coupled with one media processor. This would operate at 200MHz and take up a few square millimetres of silicon.
“The HDTV decoder would probably be a series of 750s possibly with hardware accelerators and then at the end of that you would have another 750 with multiple media processors to do the pixel processing,” said Hutton. While that sounds a significant sub-system, it would be around 900,000 gates, which is comparable to a hardwired decoder from companies such as STMicroelectronics or Broadcom. This would occupy 20 sq mm (a chip less than 5x5mm) in a 130nm process, so on 65nm that would be around 8 or 9 sq mm.
ARC has filed a patent on the interconnect, which is a direct link from the CPU core to the co-processor, and allows co-processor to control the CPU core directly by changing the program counter. This avoids latency issues that are common with multi-processor systems.
Meanwhile ARM has launched a version of its Cortex R4 for the automotive market.
The Cortex R4F adds floating point so that it can be used for the engine control and directly compete with Freescale Semiconductor's PowerPC. The single precision FPU is particularly useful in sophisticated control applications, where algorithms are often modelled in an environment such as Simulink or ASCET-SD, and code auto-generated using tools such as Real Time Workshop Embedded Coder, ASCET-SE or dSPACE Targetlink.
It also adds ECC error checking in the core to increase the reliability of systems, as designers do not need to add external ECC logic, simplifying implementation and aiding IEC61508 certification. Careful integration of ECC within the processor pipeline allows this to be achieved without the performance penalty which is normally associated with this level of protection.
For more information, visit www.arc.com
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