The world's largest chip foundry is preparing to have wafers made on the next generation 45nm wafers as early as next year.
“We will have first wafers of 45nm next year some time but we still have to ramp 65nm,” said Chuck Byers, vice president of marketing at TSMC.
“Our job is to have a viable manufacturing process for all the fabless companies. We will go to 45nm when our customers go to 45nm. The next reference flow 7.0 will be for 45nm and it's in the labs and on the roadmap but we are the last people in the chain to make money so we are going to get focussed on getting all our customers on 65nm,” he said.
Volume production is still focussed on 130nm, with leading edge customers on 90nm for production, while customers such as Altera will launch 65nm products later this year.
“We are amazed how fast 65nm has ramped,” he said. “Qualcomm for example was two months ahead of time with 65nm. We believe this is going to be a relatively smooth transition - we had all the problems at 0.13 with low K but this is the third generation of low K, the third generation of copper and it's only been the move from cobalt silicide to nickel silicide for less resistance that's significantly different.”
The company has focussed on design for manufacturing to help designers at 65nm high yield quickly to compensate for the high mask costs of the process.
“I think the challenge is going to be the return on investment and that's how do you get the yield up quickly,” said Byers. “The answer is the unified database - we have developed a database over the last two years in a patented format and we are sharing that format and data with EDA vendors.”
“By using this encrypted database with our own data we can now not only share that database with EDA partners and customers to run the tools and also identify those areas of the design that are really hotspots,” he added.
A key part of the strategy is to include data from IP suppliers in the database so that the IP that customers have bought in is included in the manufacturing simulations.
“We run IP on a prototype wafer and see how it stacks up,” he said. “We are not into selling databases, we are into selling wafers so the easier we make that process the better off we will be, and we are not going to make this onerous for the IP vendors.”
Although UMC and Toshiba have both produced wafers with 65nm FPGAs from Xilinx, TSMC maintains that it is volume production that is the key.
“We are the first foundry to have 65nm volume production rather than having tape outs or first wafers. The guts of the matter is that we are open for volume. We have 6 to 9 advanced technology customers producing volume parts on a process with yields that are pleasing to everyone. And we'll make on all comers - that's the big deal in the foundry industry.”
However, he says there are no significant challenges with scaling the technology to 45nm. “The thing that's going to kill Moore's Law isn't physics, it's fear. The sky isn't falling in,” he said.
For more information, visit www.tsmc.com
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