Include intelligent debugging data mining technologies to reduce violation noise, which is one of the most pressing RTL sign-off challenges. Nick Flaherty reports
Today’s complex system on chip designs need robust IP that can be reused across multiple devices, which means that sign-off checks that were previously performed at the netlist implementation stage now need to be performed on the RTL design.
Traditional static lint and CDC tools have not been effective at ensuring that the RTL code is of the highest quality.
Cadence Design Systems has expanded its JasperGold Formal Verification Platform with the latest formal verification techniques.
The JasperGold Superlint and Clock Domain Crossing (CDC) Apps provide formal analysis technologies that improve IP design quality by reducing late-stage RTL changes by up to 80 percent and reducing IP development time by up to four weeks.
The JasperGold RTL sign-off apps include intelligent debugging data mining technologies to reduce violation noise, which is one of the most pressing RTL signoff challenges today.
The apps are fully integrated with the JasperGold Visualize debug environment that uses proven formal analysis to increase debug efficiency for RTL designs and use Cadence’s existing formal capabilities to improve waiver handling.
Designers can now perform sign-off with robust, reusable and CDC-clean RTL code in the verification and implementation phase, shortening overall time to market and significantly improving design quality.
“Ever-increasing project schedule and IP quality pressures make effective RTL sign-off an important part of the development process,” said Dr Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Building upon the proven JasperGold platform, Cadence is bringing its industry-leading formal technology to RTL sign-off, giving logic designers the ability to develop more robust and reusable IP code in a significantly shorter amount of time.”
In the Superlint App, Cadence has combined traditional RTL linting and formal verification capabilities, deriving functional checks from the RTL automatically. Similarly, the CDC App offers a metastability injection flow for rigorous CDC verification in either the JasperGold formal or Xcelium Parallel Simulator environments for more comprehensive sign-off.
“We’ve been using the JasperGold Superlint App at ARM for more than a year, and we’ve had success with improving RTL signoff and shortening time to market. With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage,” said Hobson Bullman, vice president and general manager, Technology Services Group at ARM.
“We’ve identified functional and structural CDC issues earlier in the RTL signoff phase using the JasperGold CDC App. Eliminating these bugs earlier in the process has increased the quality of our designs and saved us between two and four weeks on the design and verification time for each of our IP,” said David Vincenzoni, design manager at STMicroelectronics.
The Superlint and CDC Apps for RTL Signoff also support the company’s broader System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.