Cadence Design Systems has developed a new register-transfer level (RTL) power analysis tool for system-on-chip (SoC) design teams to analyse power consumption quickly and accurately during design exploration.
The Joules RTL Power tool uses a multi-threaded architecture to produce results 20x faster in time-based RTL power analysis when compared to other methods.
The new tool uses rapid prototype technology from the Cadence Genus Synthesis engine to handle designs of up to 20 million instances overnight with gate-level accuracy within 15% of final power as signed off in the company’s Voltus IC Power Integrity tool. In addition, the Joules RTL Power Solution integrates seamlessly with the Palladium emulation platform and the Stratus High-Level Synthesis (HLS) platform for early system-level power analysis and optimisation.
The Genus synthesis technology allows physically aware clock tree and datapath buffering for accurate RTL power estimation, while the power analysis is parallelised across multiple CPUs to accelerate the exploration of the design space to find the lowest power options.
Multiple stimulus files can be analysed simultaneously and each stimulus file can be time-sliced into frames to enable time-based power reporting. The user can select individual frames to zoom in on power-critical periods of the simulation, and multiple stimuli for different design hierarchies can be merged to mimic full SoC traffic and power consumption. This enables design teams to easily analyse critical power problems.
The power analysis results can be reported at the bit level or register level and may be categorised based on logic cell type, design hierarchy, clock domain, power domain or timing mode. This gives the team more visibility of the options in the design space, and the tool can be used within the Palladium Dynamic Power Analysis for more accurate time-based power calculations. This provides enhanced production-correlated peak and average power analysis, enabling design teams to analyse system power of software running on hardware early in the development cycle.
“We see a significant opportunity to improve the capacity and accuracy of power analysis during system-level design exploration,” said Dr Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “The Joules RTL Power Solution combines the strength of our production implementation flow with parallel stimulation file processing to offer a power analysis solution that is fast enough for system-level analysis, yet correlates well to signoff results.”