Cloud platform provides quick access to targeted vendor reference designs, tools and models. Nick Flaherty reports
Mentor Graphics has teamed with key industry partners to form the HyperLynx Alliance for free access to virtual reference designs plus tools, design data and identified best-practice methodologies for difficult SerDes and DDR design and verification challenges.
New high-speed protocols are increasingly difficult to design and verify at multi-gigabit speeds, and the Alliance cloud platform provides quick access to targeted vendor reference designs, tools and models, allowing engineers to evaluate and trade-off device parameters using recommended verification methodologies and sample channel designs.
The alliance uses the HyperLynx tool suite for high-speed design and verification, deployed on cloud-based virtual labs to accelerate time to productivity.
The virtual lab series uses partner models and reference designs with the HyperLynx tool suite to demonstrate ideal design methodologies to address difficult high-speed printed circuit board (PCB) SerDes and DDR design challenges.
The virtual labs reduce engineering time and costs associated with evaluation design tool requests and design case setup which could take days or weeks. The labs walk through a recommended design process, helping engineers formulate their own methodologies and enabling them to evaluate trade-offs to improve overall system performance.
“Mentor Graphics and our partners are committed to share specific design approaches helping to educate the PCB design engineering community to remove problematic high-speed DDR and SerDes design bottlenecks,” said A J Incorvaia, vice president and general manager of Mentor Graphics Board Systems Design Division.
“Many of today’s design teams may be unprepared to meet today’s high-speed design issues due to limited experience, design know-how, and immediate access to the latest design software, IC and hardware technologies. The HyperLynx Alliance was created to serve the needs of today’s PCB design engineer – with real-time access to tools, technologies and support to remove the uncertainty of today’s most daunting high-speed design issues.”
Virtual labs include the complete HyperLynx design environment, partner IBIS-AMI electrical models, a reference design for test cases, and a step-by-step instruction guide. Each HyperLynx virtual lab can be completed in a few hours and is available as a future resource for users during real design and implementation stages.
All this has been co-developed with industry vendors including Altera, PMC-Sierra, Samtec, and eASIC. Virtual Labs from PMC-Sierra, Samtec and eASIC will be available in early 2015.
“We are pleased to be the only FPGA vendor that is part of the HyperLynx Alliance, which provides a great resource to design engineers by allowing them to exchange known-good high-speed design practices and methods,” said Raj Patel, senior manager of midrange products at Altera. “These jointly developed virtual labs showcase a number of leading-edge technologies featured in Altera FPGAs and SoCs, like DDR3/DDR4 memory interfaces running up to 2666 Mbps and SerDes links operating up to 28 Gbps. The virtual labs will help the engineering community quickly gain the expert knowledge required to successfully complete their designs on-time and under budget.”