Complete digital and sign-off reference flow

Jon Lawson

Cadence Design Systems has developed a complete digital and sign-off reference flow for Imagination Technologies’ PowerVR Series7 graphics processing units (GPUs). Using the integrated Cadence reference flow, the full synthesis and implementation of 5.5M instances was completed in two and a half days, half the time of previous Cadence design flows. The new flow also achieved an average area reduction of three percent, while achieving a seven percent area reduction on Imagination’s most complex block.

“As a leading graphics technology, PowerVR GPUs are found inside some of the world’s most popular products,” said Tony King-Smith, EVP marketing at Imagination. “Our customers care deeply about the speed and footprint of our highly scalable GPUs in their production chips. We collaborated with Cadence to help them create this reference flow based on Cadence digital and signoff tools that help our licensees bring to production smaller, faster chips in less time.”

The simple, single-pass Cadence flow provides designers with guidelines to optimize their PowerVR GPU cores via documentation and scripts that are easy to deploy and support. The flow includes the Innovus Implementation System, a physical implementation tool that incorporates a massively parallel architecture. This enables SoC developers to deliver high-quality designs with highly competitive power, performance and area (PPA). It also includes the Genus Synthesis engine for RTL synthesis and physical synthesis that mitigates productivity challenges faced by RTL designers. This helps deliver up to 5X faster synthesis turnaround times and up to 20 percent datapath area reduction, while scaling linearly beyond 10M instances.

Using the Cadence Tempus Timing Signoff Solution provides a complete timing analysis tool that reduces signoff timing closure through massively parallel processing and physically aware timing optimisation, while the Conformal Equivalence Checker enables the verification and debug of multi-million-gate designs without using test vectors to speed up the development. 

The final element of the reference flow is the Quantus QRC Extraction, a next-generation parasitic extraction tool that is production proven and provides faster runtimes for single- and multi-corner extraction and best-in-class accuracy versus the foundry golden model.

“We see a significant opportunity for our joint customers to achieve improved PPA using the new Cadence digital and signoff reference flow on PowerVR GPUs,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “By focusing on the complex needs of today’s designers, we successfully created an optimal flow for PowerVR that surpasses the results of previous flows and enables our many customers using PowerVR GPUs to bring reliable, innovative designs to market more rapidly.”