Processor that supports advanced manufacturing processes including TSMC 16-nanometer FinFET Plus. Nick Flaherty reports
Cadence Design Systems has teamed up with ARM to deliver a complete system-on-chip (SoC) development environment supporting the new ARM premium mobile IP suite that incorporates the latest ARM Cortex-A72 processor, ARM Mali-T880 GPU and ARM CoreLink CCI-500 Cache Coherent Interconnect solution.
Cadence has developed a reference flow for the ARM Cortex-A72 processor that supports advanced manufacturing processes including TSMC 16-nanometer FinFET Plus. Also available with the Cadence flow is high performance ARM Artisan physical IP and ARM POP IP for the ARM Cortex-A72 processor and ARM Mali-T860 and T880 GPUs, enabling designers to meet aggressive processor performance and power goals.
“The ARM Cortex-A72 processor sets a new standard for delivering a premium mobile experience and is expected to be the highest performing CPU technology for mobile SoCs,” said Noel Hurley, general manager, CPU group, ARM. “Our continued collaboration with Cadence helps our mutual customers differentiate themselves and deliver innovative, industry-leading solutions for mobile devices.”
The Cadence development environment includes digital and system-to-silicon verification tools and IP that support the ARM premium mobile IP suite, speeding time to market for complex, high-end mobile designs. It collaborated with ARM to target optimal IP for the premium mobile market by defining ideal reference flows from RTL synthesis to final sign-off.
The flow is proven by internal usage at ARM and includes Encounter Digital Implementation System, Encounter RTL Compiler, multiple Encounter Conformal products, Tempus Timing Signoff Solution, Quantus QRC Extraction Solution, Voltus IC Power Integrity Solution, and Physical Verification System. It has also integrated its Palladium XP Series hardware emulator and ARM Cortex-A72 Fast Models to provide 50X faster OS boot-up and 10X speed-up, as compared with the previous emulation-only solution.
The hardware-software co-development, synchronised cycle-accurate hardware/software debug support and Dynamic Power Analysis (DPA) helps optimise the balance between power consumption and expected performance using realistic software loads.
The integration of its Interconnect Workbench and ARM’s CoreLink CCI-500 interconnect matches automatically generated testbenches to the many possible configurations of the ARM IP. These testbenches are used to perform cycle-accurate performance analysis of the interconnect sub-system, optimizing device performance and speeding time to market.
“We collaborated closely with ARM to co-optimize our advanced digital implementation and signoff solutions, system-to-silicon verification tools and IPs with the ARM Cortex-A72 processor, and we’re already seeing excellent results with early high-end mobile customers,” said Dr Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence. “In addition, we worked together to ensure that the Cadence flow allows customers to integrate the ARM Mali-T880 GPU and ARM CoreLink CCI-500 to achieve optimal results at advanced process nodes. The system-on-chip (SoC) development environment supporting the new ARM premium mobile IP suite has been thoroughly tested so that designers can adopt these new technologies with confidence.”