Cadence Design Systems has launched its next generation of Tensilica’s Fusion G3 digital signal processor (DSP), a multi-purpose, high-performance DSP for compute-intensive system-on-chip (SoC) designs.
The Fusion G3 very long instruction word (VLIW) DSP is designed to be easy to program in C or C++ for automotive, consumer, internet-of-things (IoT) and industrial applications. The core consists of a 128-bit, 4-slot VLIW architecture with a high performance 11-stage DSP pipeline. Quad 32-bit integer MACs and quad single precision 32-bit floating point Fused Multiply Adds (FMAs) or MACs for compute-intensive applications including mid- to high-end audio pre and post processing, radar and low end image processing.
“As we continue to broaden our customer base, we are solving a wider range of SoC challenges,” said Steve Roddy, senior group director of product marketing for Tensilica in the IP Group at Cadence. “The flexibility of the Fusion G3 DSP is perfect for customers running a diverse set of software applications. With advanced development tools including auto-vectorisation and extensive library support, the G3 provides our customers with an easy development flow and higher performance out-of-the-box for their next-generation applications. Even those with extensive floating-point performance requirements can quickly port existing code to the Fusion G3 DSP with the optional Vector Floating-Point unit.”
The Fusion G3 expands the multi-purpose Fusion DSP product family introduced in 2015. When compared to the Fusion F1 SP, the G3 shares the same base Xtensa instruction-set architecture (ISA), while adding richer and higher throughput DSP instructions for more compute-intensive applications.
“Cadence has long supplied function-specific DSPs for audio, imaging/vision and baseband signal-processing workloads,” said Mike Demler, senior analyst of market researchers The Linley Group. “In fast-evolving markets like automotive and IOT, however, where DSP requirements are known to be changing, a narrowly-focused DSP is not always the best choice. In these markets, there is an emerging demand for high performance, multi-purpose DSP IP which supports a wider range of data types and operations, including both fixed and floating point. A single, extensive, DSP instruction set architecture (ISA) that handles many different compute-intensive signal processing tasks, can future-proof SOC designs in fast changing markets.”
Combining high-performance signal processing with configurability and extensibility allows significant customer flexibility in hardware and software design choices. The Tensilica Fusion G3 DSP was co-designed with a lead customer and has already been taped out in silicon earlier this year. The Fusion G3 DSP will be available for broad licensing in October 2016.
Tensilica processors have been licensed by 17 of the top 20 semiconductor vendors, have over 250 licensees, with 1000s of different cores in silicon. The Xtensa architecture is one of the most popular licensable processor architectures, shipping over 3B cores in 2015, in products spanning sensors to supercomputers.