Altera's 40nm Arria II GX FPGAs have successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG Workshop and are now included on the PCI-SIG Integrators List, making them only mid-range FPGAs to be compliant with the PCI Express (PCIe) 2.0 specification. The devices achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.
The Arria II GX FPGAs have integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device. The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. This IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, senior director of component product marketing at Altera. "They offer 25 per cent higher performance, up to 50 per cent lower price and up to 50 per cent lower power compared to competitive FPGAs."
The FPGAs are currently shipping and are targeted at applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to sixteen 3.75Gbit/s transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM.
For more information see www.altera.com/pr/products/ip/iup/pci-express