Altera has revealed architectural and product details of its Stratix 10 FPGAs and System on Chip devices, combining a new routing architecture with 3D packaging of transceiver die and a 64bit embedded processor core.
A key new element in Stratix 10 is the HyperFlex architecture which is enabled by using a 14nm process. This adds registers throughout the routing fabric to provide faster links between logic blocks and more design optimisation options such as register retiming and pipelining that are not practical in conventional FPGA architecture. This allows the delay between blocks falls from 3.5ns to 1.2ns, allowing design speeds of over 800MHz.
With up to 5.5m logic elements, the devices are aimed at the next generation of communications, data centre, IoT infrastructure, military and high-performance computing systems.
But the architectures also makes use of Intel’s 3D packaging technology that allows up to 144 different transceiver die to be added to the base FPGA fabric for different applications.
Intel’s proprietary EMIB (Embedded Multi-die Interconnect Bridge) technology provides Stratix 10 devices with a path to support higher transceiver rates up to 56 Gbps, emerging modulation formats such as PAM-4, communications standards such as PCIe Gen4 and Multi-Port Ethernet and other capabilities such as analogue or high-bandwidth memory by adding the different die on top of the FPGA substrate.
All the Stratix 10 devices will be available with an integrated 64-bit ARM quad-core Cortex-A53 hard processor system (HPS) that runs up to 1.5GHz with a rich feature set of peripherals, including a system memory management unit, external memory controllers and high-speed communication interfaces. This allows architects too use Stratix 10 SoCs in high-performance systems to enable hardware virtualization, while adding management and monitoring capabilities, such as acceleration pre-processing, remote update and debug, configuration, and system performance monitoring.
Security is a key consideration in embedded designs, and the Stratix 10 FPGAs use a Secure Design Manager (SDM) which delivers sector-based authentication and encryption, multi-factor authentication and physically unclonable function (PUF) technology.
Altera has partnered with Athena Group and IntrinsicID to deliver world-class encryption acceleration and the PUF IP that generate unique random numbers from the silicon that can be used as encryption keys.
Altera’s has also updated its Spectra-Q engine within the Quartus II design software software to make use of the performance, power, and area saving benefits of the HyperFlex architecture, while improving designer productivity and time-to-market.
The Quartus II software extends Altera’s software leadership with new capabilities that will deliver up to 8X compile time improvements, versatile and fast-tracked design entry, drop-in IP integration, and support for OpenCL and other higher-level design flows.
Customers can start Stratix 10 designs today using the Fast Forward Compile performance evaluation tools. Engineering samples of Stratix 10 FPGAs and SoCs will be available in the autumn of 2015. Embedded software developers can use SoC virtual platforms from Mentor Graphics to accelerate the FPGA embedded software development.