Design for Manufacturing points the way to overcoming chip problems

Paul Boughton

Getting a good yield from the latest 90nm and 65nm silicon manufacturing processes is still a struggle, and leading edge designers looking at 45nm designers are seeing even more problems.

As feature sizes get smaller, leakage currents increase, defects such as hillocks, bridges and voids create short and open circuits and yields plummet. Using data from the foundries and the best design practice can dramatically increase yields and company profitability.

The UK’s National Microelectronics Institute recent seminar day on the topic, with speakers from the UK, Ireland, Holland, and the US, looked at the requirements for design for manufacturing, from the basic chip design to the foundry and putting the devices onto boards.

This is no small matter. At 65nm, there is 1km of wire interconnect per square centimetre, and the wire delays at 300ps are many times the transistor gate delay of 53ps. And with clocks running up to 10GHz, the wavelength of emissions is 32mm, which puts induction effects inside the chip rather than outside.

All these issues impact on the yield, and tackling these in the design stage through DfM can make a substantial difference to getting the chip out on time and its profitability.
An increase in yield of just 10percent can increase the profit of a high volume product by US$50m a year, says Marco Casale Rossi, Product Marketing Manager for the Implementation Group at EDA tool vendor Synopsys.

“DFM is not a new concept,” he said. “When I started at ST Microelectronics 20 years ago DFM was just starting. This was the first time that some one tried to check the manufacturability of a design before actually making it.”

“Now the gate oxide at 65nm is three to five molecules of silicon dioxide, and the difference is the difference between high performance and low power,” he said. “Just one atom difference means a difference of 30percent in performance of reliability, and even in interconnect we are talking about a few atoms, and that is causing voids or hillocks that can become bridges between lines.”

“This is why DfM has become so popular recently, but DfM runs from the beginning to the end of the deign flow and all stages are influenced by DfM techniques,” he said.

Around 35percent of the yield is influenced by the design, including issues such as leakage current with only 10percent from the defects in the process and 10percent from the lithography.

Techniques such as adding an extra via to a connection, extending wires around via sites and spreading wires to minimise the risk of shorts. But there are also issues with the new techniques of lithography, where Optical Proximity Correction uses straight lines already in the design to improve the accuracy of the lithography. But that creates a trade off where you can only spread wires so far. A key factor is the critical area – not the size of the die but the size of the parts that are most sensitive to defects. The critical area can be reduced by separating wires, making one big wires into lots of thinner ones, and making sure critical elements are not next to each other. All of this should be done without increasing the die size if possible, although there is a trade off where increasing the size of the die, and therefore the cost, can be compensated for by increasing the yield. That is a complex optimisation with many factors.

Research at Edinburgh University has tackled that by modelling many of the factors involved to turn them into equations rather than simulations, using a combination of the critical area and yield curves.

In this way the optimum window for the design can be located. This lead to a tool called EYES which has been commercialised by a university spin off called Prediction Systems and is being used by three out of the world’s top 10 semiconductor makers.

“Critical Area is a measure of how robust the circuit is and you have different critical areas for different defect sizes,which are used with different size distribution,” said Anthony Walton, one of the researchers at Edinburgh who developed the technology.

“This depends on the fab and is different for every layer of the design.”

The EYES tool takes around 4096 samples of the chip and plots the yield of different areas to help designers reduce the vulnerability of the design to yield issues, and this design led approach is vital.

Some DfM is handled by the foundry using the GDSII data to improve the yield, called Design Rule Checking (DRC) correction, but this can be limited as you can’t go back and check the impact on the timing.

Making the changes at the design stage, rather than in the foundry, is vital, says Rossi at Synopsys.

Issues like leakage current are also a vital part of yield. Making sure the chip hits is power budget is difficult as more current leaks away even when the chip is off.

“The only way to do that is change the way you address power, which is a vital part of the yield,” he said.

He points to Intel’s recent introduction of a 65nm 70Mbit SRAM cell. Moving to a low power 65nm process increased the cell size from 0.57µm2 to 0.68µm2, and reduced the chip from 70Mbit to 50Mbit. But using other design techniques, such as a 'sleep' transistor to switch off different banks of the memory allowed the design to stay at 70Mbit and reduce the leakage current by a factor of three.

“You need data but you can get some of that from the ITRS roadmap but if the foundry can provide data more tuned to the process it really helps,” he said.

Dublin-based design house Silicon Software and Systems (S3) has been tackling these problems for several years. It has done 22 90nm designs and four 65nm designs for companies such as Philips.

“There can be maturity gap between the technology that’s available and the CAD tools,” said Flavio Cali of S3. “DfM has to be integrated into the design flow as early as possible, optimising for yield as early as possible.”

S3 uses a combination of Magma Desing’s BlastCreate and BlastFusion for designing the chip, with SoC Encounter from Cadence Design Systems and calibre from Mentor Graphics for the layout. It is in these two latter tools that the DfM is integrated into the design flow, optimising the wire lengths and separation and vias with Encounter, and analysing the result with Calibre to re-verify the timing.

“If the fixing is to be done at GDSII level that is just polygons and you can’t go back and re-verify the timing,” said Cali. “DfM has to be seen in the same light as timing verification, signal integrity or power closure,” he said.

This is all very well but the foundries do not give out the defect density data that is needed for many of the tools to make yield decisions.

“Yield by design is transitory,” said Doug Pattullo, field technical support manager of the world’s largest foundry, TSMC, based in Holland. “If you want to go to the latest node you are working on at the edge so there are things you can do to improve the yield. As the process and tools become more mature the need for Design for Yield reduces.”

Instead of providing fundamental data, TSMC has used its knowledge of the process to provide ‘Advisories’ that are design rules over and above the process design rules to help improve yield. The companies, such as Cambridge Silicon Radio, can choose to adopt these advisories and decide whether the area penalty is worth the yield increase.

These are included in a Reference Design Flow of tools from Cadence and Synopsys,but over and above that there are DfM utilities with extra tools to describe parasitics, well proximity effects and transistor spacing that are run once the layout is complete.

These highlight potential yield problems so the designer can fix them, then re-run the timing verification. There are also tools to analyse the amount of metal in each area to make sure it is balanced for the chemical metal polishing (CMP) part of the process.

TSDMC also provides a tool for Yield Sensitivity Analysis (YSA) that quantifies the improvements that would come from doing the yield enhancements. This produces a GDSII map and a text report, and customers use this to decide whether they want to take the extra time to make the changes and add more area to the die to enhance the yield.

“Why not provide the (defect) data, I can hear the question already,” said Pattullo. “We would like to and may in the future, but at this moment it’s data mining from the database and it really requires some on with expertise to interpret the results. The tools (that TSMC provides) are not cheap and it changes and some of the rules may become obsolete.”
That’s why DfM is a transitory thing, he says.