Managing PCB signal quality

Paul Boughton

Driven by advances in lithography, IC switching speeds continue their progressively-faster march. At the same time, escalating clock speeds result in much less forgiving timing margins.

The techniques for managing these effects can be broken into three broad categories, sometimes referred to as ‘The Three Ts’:

  • Technology. Select driver technology that’s fast enough to meet your functional needs, but as slow as possible.

  • Topology. Select topologies that meet timing requirements while minimising the impact of signal reflections.

  • Termination. Manage signal reflections using passive components.

Sounds easy, right? The problem is that there are thousands of such choices to be made when designing a printed circuit board (PCB), and trade-offs must also be managed with timing requirements, electro-magnetic compatibility (EMC), power consumption and manufacturing costs.

Moreover, the trade-offs within each of the three Ts include several more sub-variables. When making topology decisions, for example, trace impedance must be considered, along with the topology style (eg, multi-drop, branched T, H-tree, star, etc.), BGA breakout strategy, routing layer(s), vias, and trace and stub lengths. Termination requires multiple trade-offs, as well. After choosing among the four major termination types (eg series, parallel dc, parallel ac, or Thevenin), you’ve got to then optimise the passive component values, and nail down passive component placement. To say the least, managing signal quality is a non-trivial endeavour.

Impedance mismatches

Before we go into detail on the ‘Three Ts’, it’s important to address impedance mismatches at a more general level.

Reflections occur at any impedance discontinuity, including variations in board stackup, trace-width variations, BGA breakouts, stubs, vias, loads, connector transitions, or large power plane discontinuities. Some reflections – if significant enough – cannot be resolved using the Three Ts.

For this reason, careful pre-layout impedance planning, with a tool like HyperLynx’s Stackup Planning tool, shown in Fig.1, is a critical part of a proactive impedance-control process.

The significance of a reflection is impacted by a number of factors, including the impedance difference, the length over which the impedance difference occurs relative to the overall length of the transmission path, and your technology’s tolerance for noise.

Triage by technology

There are several strategies for dealing with non-ideal routing. The first is to know which nets can accommodate poor routing and which cannot. A three-tier ‘technology triage’ strategy works well: divide nets into those that are ‘signal-integrity-critical’ (clocks, strobes, and other signals that require clean edges); those that are ‘timing-critical’ (address, data, and signals that can have non-ideal edges but must align with timing requirements); and signals with driver edge rates that are faster than 5 nanoseconds. The remaining signals can be ignored from a signal integrity standpoint.

A quick look at the effect of fast driver edge rates is instructive. Fig. 2 shows the effect of increasing driver edges on the same 5-inch trace.

The 10ns and 5.0ns drivers produce clean receiver waveforms. The faster 2.5ns and 1.0ns drivers, however, produce reflections and ringing on the yellow and red receiver waveforms.

Topology, signal integrity, and timing

Signal-integrity problems tend to disappear when nets are short relative to how fast they are driven, as reflections settle much more quickly. From the fastest 1.0ns waveform in Fig.2, the reflections eventually smooth out at a half inch trace length.

Though academically instructive, a health-conscious engineer certainly wouldn’t want to specify more than a few carefully planned high-speed nets with a half inch maximum length requirement! We’ll discuss additional alternatives when we get to the third ‘T’.
Sometimes, departures from ‘good-practice’ routing can actually be a key to resolving signal-integrity problems.

Consider the case of a clock with multiple receivers, each of which is skew-sensitive (the clock must arrive at each receiver at close to the same time). In this case, a daisy-chain route may not be ideal because it delivers the signal to each receiver serially, inherently creating skew.

Here, a superior scheme may be a ‘star’ pattern in which each receiver (or small subsets of receivers) has its own routing branch. Each receiver can be placed approximately the same delay length from the driver, and each receiver is considerably more isolated from other receivers than on a daisy chain.

Underscoring the interrelationship and trade-offs associated between the Three Ts, however, star routing introduces several new problems. Multiple branches present the driver IC with a low impedance, requiring it to dynamically sink and source significant current. In practice, you may need to use a stronger driver technology for this topology.

For example, a Spartan-3 LVCMOS33_F_24mA driver instead of a LVCMOS33_F_8mA, as shown in Fig.3.


As a general rule, any line with an edge rate faster than about 5 ns on nets running longer than an inch should be considered a candidate for termination. While reducing costs is important, the associated signal quality benefits is critical – impacting whether the product works at all.

The remainder of this article will focus on termination strategies for various trace topologies and design requirements.

What type of termination to use

The classic methods of terminating digital transmission lines are well known. You can terminate the source, the far end, both, you can employ ‘distributed’ terminations at several locations, or you can use two parallel dc terminating resistors pulled to opposing power supplies to achieve a specific dc bias for Thevinin termination.

Basic guidelines:

  • Source termination is useful in point-to-point/one-directional connections.

  • Far-end termination is useful in multi-point connections.

  • Distributed termination can be helpful if you have a plug-in system with variable configuration.

Each of these techniques has advantages and disadvantages. Parallel dc termination is the simplest, both from the standpoint of component count (only one; built into Spartan-3 FPGAs) and the choice of value (equal to the line impedance), but it burns the most power and may unacceptably load the driver IC. Ac termination requires an additional component (more expensive, extra board space, less reliable) and more engineering work (finding the optimal capacitor value), but reduces power consumption.

Series termination creates a voltage ‘plateau’ that persists until a reflection is received back from the end of the line, so series terminators do not work properly from a timing standpoint unless the receiver ICs are clustered near the end of the net, as shown in Fig. 4.

There are several ways to terminate at a junction or star connection. One possibility is a series termination at every driver. This has the advantage of reducing settling time at the receiver, while consuming a minimum amount of power. Several conditions must be met for a single series termination strategy to be effective.

First, each branch must be close to the same length; otherwise, reflections coming back from each branch are not in synch and end up ‘bleeding’ from branch to branch.

Also, each branch must be the same impedance (or close), or it will be impossible to choose an effective single resistor value. If branches are longer than three-quarters of an inch, it makes sense to make their parallel impedances equal to the inbound line impedance from the driver. You can also terminate at the junction itself by changing the trace impedance, or using parallel dc termination – both dampening reflections quickly, and attenuating the signal.

The appropriate choice depends on the network topology and signal direction. For nets that have complex routing patterns, it may be difficult to find a termination scheme that works even in theory. This is where a ‘what if?’ simulation tool can be an indispensable ally in comparing alternatives.

As long as clock speeds continue to climb, and driver edge rates grow progressively faster, hardware engineers will need to budget between 10to40percent of their project schedules for the process of managing signal quality, timing, EMC, and power.

To mitigate potential problems, a software simulation tool with virtual prototyping capabilities can be an indispensable ally.

What if?’ simulations

There are several features to look for in good analysis software. One is the ability to run ‘what-if?’ simulations easily, and as early as possible in the design cycle. Another helpful feature is a tool’s ability to recommend strategies and termination values. HyperLynx, for example, includes a ‘Terminator Wizard’ that can automatically analyse standard topologies, suggesting optimal termination strategies and component values. This feature can be coupled with a quick whole-board scanning mode that can make recommendations and flag violations for an entire PCB in just a few mouse clicks.

Armed with a solid board-triage process, the ‘Three Ts’ covered in this article and your new analysis software … you’ll not only be ready for today’s technology, but you'll
be in a good position for what’s coming down the pike
as well.

Bill Hargin is with Mentor Graphics. For more information, visit


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