Nick Flaherty talks to Michel Brillouet, Deputy Director for Research at French Atomic Energy Commission/LETI about the future of silicon chip design.
Leti is a laboratory operated by the Technology Research Directorate (DRT) of the French Atomic Energy Commission (CEA). It is one of the largest applied research laboratories in electronics in Europe.
Its mission is to help companies increase their competitive position by technological innovation and transfer of its technical know-how to industry. It devotes about 85 per cent of its energies to final research, with partners outside CEA.
It has 10 000 square metres of clean room in Grenoble, France, with a budget of E200m and access to other CEA resources, namely nuclear reactors, accelerators, analysis and characterisation resources. It employs more than 820 people and 567 other non-CEA staff, working with 130 industrial partners within the framework of about 500 contracts. Leti registered 153 patents including 64 for silicon technology, 48 for healthcare information systems, and 41 for optronics.
Question: Commercial silicon chip designs are starting on 65nm process technology today. How long before we move to the next generation of lithography and what will it be?
Michel Brillouet: We are starting development of 45nm and thinking about the next node, which I expect to be 32nm. As long as there’s an incentive to scale the transistors it will be done, but there’s also another factor at work, which I call More than Moore, with added value in RF, MEMS, power sources, biochips
Q: There are various techniques being proposed for the 32nm generation of lithography such as extreme ultraviolet (EUV) What is your view?
Brillouet: EUV will not happen because of development such as immersion. Here, liquid between the lens and wafer and you can increase the resolution and increase the numerical aperture (NA), but there are problems with bubble defects and polarisation effects. But this means 193i (the current 193nm technology using immersive techniques) will go to 45nm and probably to 32nm.
EUV is possible for 22nm and 16nm nodes with a 30nm wavelength. There are a lot of technology issues to be solved in the source, mask and optics and making it work is as complex as making the mirror of a telescope.
Then there’s maskless lithography. If you have a technology where you can write your design with a beam. For low volume it could be useful but the throughput is extremely low.
Then there are techniques such as resolution enhancement where you play with the intensity, phase and coherence of the light, and Optical Proximity Correction,(where you use nearby elements on the mask to increase the accuracy of the lithography) but this costs hours of compute time and increases the mask cost a lot.
Q: How do we get around these manufacturing problems?
Brillouet: We need a new transistor architecture. You have to squeeze the gate and channel more and more, so there are new structure with multiple channels and multi-gate designs. It’s very complex and people are afraid to put into manufacturing and these will probably be introduced at 32nm and not before.
High K materials are not mature and are also delayed until the 32nm node, and then there are techniques to stress the silicon to lower resistance and increase the current. We will see stretched silicon in the 45nm node in 2009, and then the multiple gate FETs at the 32nm node in 2012.
Q: The move from 200mm to 300mm wafers caused a huge shift in the industry. Will 300mm be the limit for the foreseeable future?
Brillouet: The move to 450mm wafers will come from DRAM but that's very costly and I’m not sure DRAM alone can fund the move to 450mm wafer size
Q: What are the limiting factors?
Brillouet: Interconnect is probably more then half the effort for having a CMOS technology available with 6 to 10 layers, from short range at the transistor gate level, to capacitative effects at the medium range that need low K materials and RC effects at the global range that need copper.
With low K materials you have problems at every stage of your lithography. It’s brittle as well and that's why five years ago we were very optimistic, seeing values 5 to 10 times that of silicon dioxide, but now it just a factor of two.
Copper resistance is also getting worse and we have to address that. It's very difficult to get an increase in performance just by changing materials. What you need is a change in the design as well.
Q: What about the added value and accelerating Moore’s Law?
Brillouet: You can put bulk acoustic wave filters in a BiCMOS circuit to have the filter on chip for WCMDA, or use a MEMS switch on chip for antenna switching. But that adds lots of mask steps
and it’s not clear if it's suitable for manufacturing.
Codesign of the electronics and the sensor is key. For example at LETI bringing together designers and technology people is key and it more important for this approach.
For example in health care you may think of silicon technology in the future in a totally different way for example with a lab on a chip, using electrowetting. Before it comes to manufacturing it takes basically 15 years and we are in that scale now.
Q: Will CMOS run out of steam?
Brillouet: There is also no emerging device that is applicable to logic processing that is better than CMOS. The point is that if you are thinking about new devices with feature sizes of 1 to 2nm the entry point will be interface devices, for example using carbon nanotubes for GHz front end devices, and these things wil happen in 10 to 15 years. The next step will be memories, with molecular memories with a memory feature as part of the structure of the molecule.
It’s still not clear if it will be successful. That’s still in its infancy but it could happen. For logic devices it's more difficult. Scaling will last as long as we have an economic return, and that's clearly down to 45nm and probably 32nm but beyond that I don’t know.
If you look at aircraft, we got to supersonic speeds with Concorde but the fact that we are not going faster doesn't mean we are not innovating, it's just in a different direction with longer range and larger aircraft.
More and more we have to take care of software and the usage of the devices and there is not clear roadmap for that. For example in multicore systems you have to have the operating system and debugging to take advantage of the technology.