The boundary-scan test standard (IEEE 1149.1) has come a long way since it was first conceived by the Joint Test Action Group (JTAG) more than a decade ago. The JTAG committee set out to define a simple, low-cost embedded test method that would be particularly useful for dense circuit boards where physical access to device pins and test pads was vanishing.
Since its acceptance as an industry standard, the four-wire boundary-scan interface has earned a reputation as a versatile infrastructure technology at the device and board level. In recent years, developments have opened the door for boundary scan to a wider range of applications, such as the testing of high-speed c-coupled serial buses, combinational testing with processor-based functional emulation, the concurrent programming of programmable logic devices (PLDs), design validation of Intel-based buses and others. In addition, boundary scan is coming into its own as a tool for system-level test and troubleshooting as well.
Boundary scan's versatility and flexibility is evident in its ability to combine with other test methods and technologies to create synergistic test processes that achieve greater test coverage than any individual method could on its own.
Of course, the combination of boundary scan with in-circuit testers is well established. Some boundary-scan test systems have been tightly integrated with ICT platforms so that tests developed to debug prototypes in the development department can be directly transferred to high-volume manufacturing where those same tests are applied on ICT systems. This eliminates the added step of developing new boundary-scan tests for manufacturing, saving time not only on JTAG test development, but also reducing the cost of developing ICT tests and fixtures because boundary-scan tests can offload some testing tasks from ICT. Some large designs are not fully testable with ICT unless boundary-scan is first used to reduce the number of physical test points for an ICT test fixture.
In addition to ICT, some boundary-scan test systems have recently been combined with processor-based emulation test methods. For many years the JTAG port on most microprocessors has been used by software emulators that run on microprocessors and perform functional tests.
By combining boundary-scan with rocessor-based functional emulation test on the same test system, coverage can be extended significantly (Fig. 1). This opens the door to areas of the board that previously could not be tested by boundary scan. For example, because of the access provided by processor-based emulation, functional tests controlled through the JTAG port can be executed on complex logic devices like Ethernet controllers even though these devices typically do not have embedded boundary-scan capabilities. They can be accessed by the system's microprocessor and therefore can be exercised with functional test patterns. As a result, boundary scan and processor-based functional emulation testing can extend test coverage well beyond what either test method could achieve on its own.
Boundary scan's chip-to-chip and board-to-board communications infrastructure has been appropriated by other newly emerging test and in-system programming technologies. The simple yet elegant four-wire interface of boundary scan has provided a very functional basis for a number of related technologies.
The first such technology was the IEEE 1149.4 standard for testing analogue devices. More recently though, the IEEE 1149.6 Standard for Advanced Digital Networks has been developed and ratified. IEEE 1149.6 tests and validates the design of high-speed (10 gigabits per second and greater) serial buses like Gigabit Ethernet, Fibre Channel and others with ac-coupled LVDS signaling. IEEE 1149.6-based testing makes use of, and is dependent upon, a circuit board's boundary-scan infrastructure. Even ardent supporters of boundary scan could not have foreseen this eventuality more than a decade ago when boundary scan was first being defined.
The IEEE 1149.6 standard specifies a method for applying a system's boundary-scan capabilities to test a wide variety of high-speed interconnect buses with differential signaling (Fig. 2). A boundary-scan system that supports the new 1149.6 standard can perform both its traditional test functions on the dc-coupled buses in a design in addition to the 1149.6 tests that are applied to the high-speed ac-coupled buses. These types of high-speed buses are becoming increasingly prevalent in certain types of computing and communication systems. Indeed, many types of systems such as high-speed routers and wireless basestations already feature hundreds, if not thousands, of high-speed ac-coupled serial links with differential signaling.
In addition to industry test standards like IEEE 1149.6, certain proprietary embedded test technologies are based on the boundary-scan infrastructure. Intel, for example, has developed its own Interconnect Built In Self Test (IBIST) as a next-generation test method in its new chips and chipsets. It depends upon boundary scan for chip-to-chip communications and this is integral to IBIST's ability to cost-effectively validate the design of high-speed bus structures such as PCI Express.
Soon after the development of the original JTAG standard, boundary scan's access to on-board components was soon appropriated for loading programs and data into storage or logic devices after they had been soldered onto a circuit board. Over the years, several methods for loading programs into storage devices like flash memory or for configuring programmable logic devices (PLDs) have been developed. Most recently, the IEEE 1532 Standard for In-System Configuration was devised to reduce the time required to load new configurations into logic devices. IEEE 1532 makes use of the boundary scan infrastructure to reconfigure multiple on-board PLDs concurrently, dramatically reducing the duration of the entire process and lowering production costs.
As an industry standard, boundary-scan systems supporting IEEE 1532 are able to program any PLD that conforms to the standard regardless of the supplier of a particular device. In addition, when the boundary-scan system is integrated into an ICT platform, the in-system configuration process can take place seamlessly during high-volume manufacturing.
The benefits of boundary scan are not limited to chip- or board-level testing and in-system programming operations. More equipment manufacturers are realising that individually testing each circuit board that makes up a system does not always ensure a fully functional system when the boards are plugged into a backplane, motherboard or other type of system configuration.
For example, a connector between a board and a backplane could be faulty or a circuit board might be missing or be out of place on the motherboard. Functional tests will reveal that the system is not functioning as expected, but diagnosing the problem and isolating the fault with functional tests is time-consuming, expensive and often based on trial-and-error methods. Thorough functional testing also often requires that the technician has a great deal of system expertise. In contrast, the diagnostic and fault-isolation capabilities of boundary scan are invaluable because they can quickly locate points of failure and troubleshoot the structural aspects of the entire system without a high level of system expertise on the part of the technician.
Besides playing a system-level role during design, production and repair operations, boundary scan provides many other system benefits when it is deployed as a support tool in the field. For example, boundary scan can access data and program in on-board storage and logic devices so that their contents can be quickly and easily updated in the field. Or, the configuration of PLDs can be efficiently updated to introduce new system functionality after the system has been installed.
Boundary scan can be deployed at the system level in a number of ways, but the most prevalent method today is to design-in one or more multi-drop boundary-scan gateway devices which control access to the boundary-scan paths located on individual boards, backplanes and subassemblies in the system (Fig.3). These gateway devices can be controlled by an external boundary-scan test system connected to the gateway device's boundary-can test access port (TAP).
Scanning a bright future
If during the next decade boundary scan proves its adaptability and versatility to the degree that it has during the previous one, it will be well on its way to becoming a nexus for a host of exciting and useful test, programming and diagnostic capabilities. The leading providers of boundary-scan systems will continue to invest to improve the capabilities and tools of their systems. Great strides already have been made in terms of automatically generating test patterns and programming algorithms while protecting from inadvertent electrical loads the devices, boards and other subassemblies that make up a system. In addition, highly graphical user interfaces and step-by-step assistance for new or occasional users have improved the ease-of-use of some boundary-scan systems and test generation times have been reduced from days to hours in some cases where boundary-scan design-for-test guidelines have been followed.
Reg Waller is European Sales Director of ASSET InterTech, Richardson, Texas, USA. " target="_blank">www.asset-intertech.com"