Quicklogic has admitted defeat and sees itself moving from an FPGA vendor to a provider of aintelligent bridges' over the next five years, says chief executive Tom Hart.
It is integrating more and more hardwired intellectual property alongside its configurable, one time programmable, low power VIAlink metal-to-metal array to produce customisable devices.
The current focus on linking 802.11 wireless chips with PCI interfaces to embedded systems. This is a low power approach, he says, as data can be moved to memory without waking up the host processor.
In five years time, he says he sees these bridge chips as 35percent of the business, up from some 10percent now, and 40percent in higher performance computing engines using the configurable array to implement dedicated hardware processing engines. Currently the majority of the business is in glue logic. This strategy has been driven by the success of Altera and Xilinx in the SRAM-based FPGA market.
Meanwhile Atmel is also pushing the combination of hardware and FPGA with a new family of devices.
The FPSLICII is a dynamically reconfigurable programmable SoC that integrates a 25MIPS, 8-bit AVR processor, with 36KB program/data SRAM, a hardware multiplier, peripherals and a dynamically reconfigurable FPGA, with 256 to
2300 core cells.
A single piece of silicon can implement multiple, interchangeable peripherals, computational operators, and bus interfaces, including UART, SDIO, PCI, PCMCIA, HDLC, and Ethernet.
The key is the design tools, developed by Atmel and the ReCONF2
(EU-IST-2001-34016) project with the cooperation of the Czech Academy of Sciences' Institute for Information Theory and Automation (UTIA).
The tools are the first to automate the implementation, timing, and control of the silicon-sharing process.
Previously, the design of ilicon-sharing systems was essentially impossible because, even though some FPGAs can be reconfigured during operation, until now, there have been no tools to automate reconfiguration control and timing.
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