The majority of today’s power supplies, targeting near unity power factor, employ active power factor correction (PFC) in the ac/dc front end. The PFC section, or ac/dc stage, boosts the input ac line voltage to a level, above the maximum ac line peak voltage, usually to the level of 385Vdc.

There are number of important functions and details of the architecture of modern PFC controllers that should be of interest to the designers of off-line power supplies.

Although many companies manufacture various types of PFC controllers, the architecture and structure of these chips remain very similar. Most PFC controllers employ a gain modulator, a current error amplifier (IEA), a PFC comparator, a voltage error amplifier (VEA) and a PFC pulse output driver.

The inner control loop is a current control loop, comprising the gain modulator, IEA and a PFC comparator. The outer control loop is a voltage control loop, which uses VEA as an error amplifier. The VEA output (VEAO) is also one of the gain modulator's inputs.

The inner current control loop shapes the line current drawn from the AC mains to be simultaneously proportional to the AC line voltage. The outer voltage loop keeps the PFC DC bus voltage in regulation at about 385V. It is important to note that the current control loop has a much larger bandwidth compared to the voltage control loop.

The PFC comparator-driver section of the PFC controller, is designed around the PFC comparator. The oscillator generates a saw tooth waveform and a CLK signal which is synchronised with the falling edge of the saw tooth waveform. The saw tooth waveform is designated as the ‘PFC_RAMP’ signal, also called RAMP1.

In the beginning of the cycle, the CLK high signal sets the PFC_OUT low. Once the PFC_RAMP exceeds the output of current amplifier (IEAO) level the PFC_OUT becomes high, eventually switching the external PFC transistor ON. The PFC_OUT stays high until the end of the cycle, when the CLK sets it low. Therefore PFC implements the leading-edge of regulation.

Usually the PFC chip ensures that the PFC duty cycle D and the PFC_OUT pulse never reach 100percent. This approach prevents saturation of the boost inductor. The maximum duty cycle occurs at the zero crossing of the ac line voltage.

Thus, when Vin is zero, the controller IC limits duty cycle to 98percent. For example, actual waveforms of a PFC controller from Fairchild, called the FAN4810. This is where Ch4 is the output of current error amplifier.

It is very important for the designer to set a proper value of the current error amplifier output. For example, the FAN4810 spec defines the RAMP1 valley-to-peak voltage as 2.5V. This means that by regulation, the dynamic span of IEAO voltage should be within the RAMP1 signal swing rang.

The IEA in many ICs is a transconductance amplifier. A Type 2 compensation circuit is connected to the reference voltage pin VREF, for establishing a soft-start function of PFC. At start-up IEAO rises to the reference voltage level; and as the loop comes into regulation, IEAO drops from VREF level to the operating level. This guarantees that the PFC duty cycle gradually increases from 0percent to the desired value as required by the loop, thus providing a soft start feature.

Gain modulator functionality

The central part of the PFC controller is the gain modulator and voltage error amplifier. The gain modulator generates a program signal for the current control loop, which shapes the input current. The FAN4810 PFC controller's current control loop ensures that negative voltage from the current sensor is balanced by a positive voltage across an internal Rcp resistor. This positive voltage is generated by gain modulator output current that flows through Rcp. Thus, the drawn line current (I_line) and, therefore, the voltage on ISENSE pin is forced to replicate the shape of gain modulator output. In other words, the condition: is always met. Where, Rs is the line current sense resistor and IGM is the output current of gain modulator.

To shape the drawn line current, the gain modulator employs three inputs: IAC, VRMS and VEA output. PinIAC is connected to the output of the ac line rectifier bridge through a 1MOhm resistor. The IAC current is a full wave-rectified sine wave at double the line frequency, and is proportional to the instantaneous ac line voltage. The IAC actually shapes the gain modulator output current to be sinusoidal as described by the following expression.

Voltage on the VRMS pin is a DC voltage proportional to the RMS value of ac line voltage. IGM is designed to be inversely proportional to the square of VRMS.

Why does the output current of the gain modulator need to be inversely proportional to the square of the RMS value of the AC line voltage?

Let’s assume that VEAO is constant. If the input line voltage doubles, consequently to provide the same power; input current and, accordingly, IGM should be reduced in half. When line voltage doubles, IAC also doubles, see (2). Thus to parry increase in IAC the VRMS signal should be quadruple.

VEA Bandwidth and THD

The third input of gain modulator is output of VEA, which defines the amplitude of the gain modulator's output current. Inverting the input of VEA is connected to a voltage divider for sensing PFC output voltage. In the case of the FAN4810, the FB pin is set to 2.5V at the nominal bus voltage. VEA is a transconductance amplifier with a Type 2 compensation circuit. There are two conflicting requirements for closing a feedback loop around VEA: 1) The loop should have bandwidth low enough to attenuate the 120Hz ripple voltage on the DC bus so as to decrease the total harmonic distortion (THD) of input line current, and 2) The loop should be fast enough to provide acceptable load transient response.

THD is an important factor for designers to consider. The bulk capacitor voltage ripple is displaced by 900, as compared to the line voltage, due to the reactive nature of the output capacitor.

Because signal proportional to the displaced voltage ripple feeds directly to the VEA, gain and bandwidth of this amplifier should be limited. Usually the voltage control loop crossover frequency is set in an area between 10Hz and 30Hz.

Two interesting features of the gain modulator are rarely discussed. First, the transfer characteristic provides a natural brown-out protection. The maximum gain of the gain modulator is designed to be at minimum line voltage. If the input voltage happens to be below the specified minimum (brown-out condition), the gain and, consequently, the
PFC duty cycle falls sharply, thus reducing the bus voltage.

The second interesting feature is an inherited over-current protection. The maximum output voltage of the gain modulator is limited; in the FAN4810 it is 0.8V. If, for any reason, voltage on the ISENSE pin falls below -0.8V, due to overload for example, the inverting input of IEA becomes more negative with respect to ground. Therefore, the IEAO level will increase, reducing PFC duty cycle and bus voltage, and thus limiting the output power.

PFC protection circuits

Like other controllers, the FAN4810 includes a number of protection circuits related to PFC operation. These include Over-Voltage Protection (OVP) and Over-Current Protection (OCP). A SR flip-flop, set by either PFC OVP or current limit, terminates the PFC output pulse. Therefore the OVP and OCP faults are sensed and latched every cycle.

The Fairchild device used in this example also has Tri-Fault protection. This type of protection covers the following faults: (a) FB pin is shorted to ground, (b) the line (wire or PCB trace) from PFC DC bus voltage divider to the VFB pin of the IC is broken, and (c) the top or bottom resistor in a voltage divider is open. If FB is short to the ground (a), the voltage on PFC_FB pin is below 0.5V and the Tri-Fault comparator output disables the PFC OUT pulse. In the case of a broken wire (b), an internal current source starts charging the capacitor Ctf . Then, once the voltage on the FB pin exceeds 2.75V, the OVP comparator will terminate the PFC output. Capacitor Ctf is optional and defines the time t_F to trigger the protection circuit.

For the fault conditions described in (c), OVP or TRI_FAULT will terminate the PFC_OUT pulse. The OVP protection kicks in if, for any reason, the dc bus voltage exceeds the nominal level by more than 10 per cent. For example, if the nominal bus voltage is 385VDC (2.5V on FB pin), OVP triggers if the bus voltage exceeds 423Vdc (2.75V on FB pin).

Conclusion

PFC controllers provide an important role in ac/dc designs by integrating such protection functions as over-voltage protection (OVP), over-current protection (OCP) and, in the case of the FAN4810, TriFault protection. Converters with active PFC and near unity power factor meet the ICE61000-3-2 specification requirements, alleviating a major source of concern for power supply designers.

Vinit Jayaraj is Principal Design Engineer and Victor Khasiev is Principal Application Engineer at Fairchild Semiconductor. For more information, visit www.fairchildsemi.com