The Sophia Antipolis MicroElectronics (SAME) conference in France brings together some of the leading electronics companies who have research centres in the region. Developed over the past ten years, the conference has branched out to bring in new startup companies from across Europe.

Six companies were part of the the conference, competing for the award for the best presentation and looking to build links with larger companies as partners or customers.

The vast majority of the startups featured were looking at design tools – easier to start and finance than chip makers but harder to make those big customer wins that take the business forwards.

One company that is taking a different route is nSilition from Mons in Belgium. It has developed a tool to generate data converters for system on chip designs, optimising the design for the power requirements. The founders come from companies such as STMicroelectronics and Alcatel,

“Forty-five per cent of SoCs have analogue content but it can be risky and requires a specialised design team,” said founder Theirry Delmot. “The performance of the data converter is key to any modem system, whether it is DSL, customer equipment or central office, and for mobile phones. We provide efficient reuse of designs that are technology independent and yet increase the design density to address the power consumption issues,” he said, “We can convert with speeds higher than the current technology while the power consumption is reduced. We believe we are twice as good as what you have seen on the market up until now.”

The technology is based on research at the University of Mons where the data converters do not the traditional sample and hold approach, but instead have a simple buffer to make the integration into the wider design much simpler.

While the four-strong company has developed a tool for generating the IP, it is using this tool to offer specialised designs as IP blocks, helping design teams integrate the IP into their design flow, rather than selling the tool.

Blocks have been implemented at UMC on a 180nm process running at 100Msample/s for a 10bit converter with 66mW power consumption, as well as a 150Msample/s 14bit block made on TSMC’s 130nm process consuming 250mW.

AnSyn was set up by two graduates of the University of Linkoping in Sweden in 2006 to automate filter design, but has emerged as a tool to automatically size analogue components and re-simulate large systems to improve the yield of mixed signal designs.

“There is definitely a need for tools like this, and many tools have had the wrong approach to tackle this problem with libraries of resizeable components that the designer couldn’t access,” said Emil Hjalmason, CEO of Ansyn.

“We remove the boring parts of the designer’s job – they don’t like to enforce yield requirements or simulate across hundreds of corners when re-sizing components,” he said.

The technology has been used by 50 strong Swedish startup SiCon Semiconductor for analogue to digital converters and the company is working with a large semiconductor company, he says.

The strength of the proposition won the company the award for the best startup, decided by a panel of EDA tool vendors and semiconductor companies.

Another startup, Heedsoft in Grenoble, France, has developed a tool for speeding up the simulation of analogue designs by abstracting the design to a higher level while maintaining the accuracy of the results. This is providing transistor level optimisation for validating functional behaviour for faster simulation. It can simulate a 512Kbit SRAM in two hours, compared to a traditional approach which can take over 2 days of simulation.

“Transistor level l (TLL) starts from a netlist and extracts the functional behaviour as well as the delays from the RTL model and you have the exact behaviour of the transistors for functional verification,” said Phillipe Ladagnous, CEO of Heedsoft. “This moves the verification from analogue simulation to digital simulation and brings new verification methods.”

The company has had significant initial success, with AMD using the tool in Boston and California for the past four years. Heedsoft is now setting up commercial offices in northern Europe and the US.

Meanwhile Satin IP Technologies in Montpellier, France, has developed a tool to help companies re-use the IP they already have.

VIP Lane is a Quality Management software tool that works alongside the Electronic Design Automation and Product Lifecycle Management tools in typical semiconductor design flows. Running as a web server application, it tracks and captures all parameters and objects affecting IP quality, from multiple sources throughout the IP design and integration lifecycle.

It uses a Design Quality Abstraction Layer to offer ‘checklist-driven’ design assistance in the most critical areas of design reuse: specifications, coding, implementation, verification and support of SoC integration.

“IP quality results from a number of engineering practices throughout the block life cycle, and requires careful daily management,” said Michel Tabusse, CEO of Satin IP Technologies. “Our tool automatically will go into the log files and the databases and import the parameters that are relevant for quality. It allows you to impose a design methodology through the design team without adding overhead and focus on where IP reuse might hurt.”

VIP Lane has already been used in several IP design projects at the Laboratoire d’Informatique, Robotique et Microélectronique de Montpellier (LIRMM, CNRS) and at Netheos, which develops encryption systems.

“Getting into the IP market is no easy decision for a company like us selling turnkey security solutions to final customers,” said Xavier Facélina, general manager at Netheos. “The Design-for-Reuse expertise accessible from VIP Lane was instrumental to our decision to market encryption solutions in the form of Intellectual Property blocks.” The tool also helps with verifying the quality of a design through the checklist approach.

“With VIP Lane as a key element of our IP qualification process, we identified and launched corrective actions on our Network Processor Unit that may otherwise have been ignored,” said Professor Lionel Torres, in charge of the System Level Architecture program at LIRMM. “We will standardise on VIP Lane for qualifying the reusability of our future IP blocks.”

The company is only five people at the moment, but Tabusse expects to expand to 10 next year and 20 by 2010.

Another Grenoble startup, Docea Power, is providing software for analysing the power consumption of a design early in the cycle.

Its Advance Calculation Engine (ACE) models both the capacitance and thermal resistance of a design, including the leakage power, to solve the power/temperature loop to optimise the design, rather than leaving large guard bands in the design.

It uses the idea of power state machines and linked hierarchical structures to quickly describe power and thermal behaviour of electronic components combining heterogeneous entities. This can be used with hardware and software components, analogue and digital blocks, process technologies, packages. This approach makes it easier to share IP or IC and to integrate large systems like SiP, SoC or boards.

“It’s different from the classical view,” said Sylvian Kaiser, chief technology officer. “It’s not a sign off tool, but really useful at the early stage in the design flow for ESL system exploration and power analysis.”

The tool is in ‘alpha’ test at the moment, running on Windows and Linux systems, and the next stage of testing will be in the first half of 2008, looking at a wide range of test cases, says Kaiser.

These young European companies are driving new technologies into the semiconductor market to help with all stages of the design cycle. Providing IP and tools to speed up the design process and make the end design more manufacturable is compelling, but these fledgling companies have to compete on the global stage.