UK-based ARC International has launched a family of standard definition video codecs blocks for the H.264 standard, ranging from resolutions of CIF up to the D1 resolution that we see on standard digital TV today. These are licensed to chip makers, particularly for portable, power and cost sensitive applications.

At the same time Texas Instruments has launched its latest DaVinci video chip, this time aiming high definition video coding at portable video and high volume consumer applications with a cost under $10.

The DM355 is tuned for applications such as digital cameras, IP video cameras, digital photo frames and video baby monitors with an integrated video processing subsystem, an MPEG-4-JPEG co-processor (MJCP), an ARM926EJ-S core and peripherals. The corresponding development tool, the DM355 Digital Video Evaluation Module (DVEVM), will help developers create low-cost portable, digital video devices with HD video capability.

“With this DaVinci offering, developers can add HD video functionality at a low price point and execute a quick launch of their product into the fast-growing HD market,” said John Dixon, DaVinci marketing manager, Texas Instruments. “The DM355 is tuned to provide the critical balance of price, performance and power for these aggressive markets in an effort to ensure our customers’ success.”

The processor is available in clock speeds of 216 MHz or 270 MHz, which allows for a scalable line of products. Combined, the MJCP and video processing subsystem provide the equivalent of up to 640 MHz of DSP processing performance. Other applications for the DM355 include commercial products, such as medical imaging, ultra low-cost digital video recorders and portable test equipment.

Depending on the application, the DM355 consumes approximately 400mW during HDMPEG-4 encoding and only 1mW of stand-by power. As an example, this means that consumers using DM355-based digital cameras in video mode can expect to record 80 minutes of HD video while using just two AA batteries.

However, while TI is pushing this as high definition, it is limited in scope. It supports 720 progressive screens at 30 frames per second but not 1080i, and MPEG4 standard profile (SP), not the MPEG4 part 10/H.264 that is commonly accepted as high definition video. The H.264 version will come later, says the company.

ARC comes at the problem from a different direction, saying true HD will not be needed for some years yet, but providing full H.264 encoding with all the tools in the standard.

The ARC 40xV family cores use ‘graceful degradation’ in the encoding process. Depending on the resources available – and that can be power or memory – the cores can throw out various tools and reduce the quality of the encoding to extend the battery life or the recording time – this is all up to the designer and allows systems based on the cores to be differentiated through these engineering tradeoffs.

The five cores are based on the VRaptor Multicore Architecture, each is programmable, encodes and decodes a wide range of popular video standards, and comes with optimised media processing elements including up to two 128-bit SIMD Media Processors, a dual-channel

media-optimised DMA engine and separate

multi-standard encoding and decoding accelerators, very similar to the TI approach, but it also includes a programmable motion estimation accelerator and the SoC development tools.

The cores occupy a tiny fraction of a chip – taking up just 5sq mm in a 90nm process including the memories.

For more information, visit www.arc.com or www.ti.com