David Barry looks at a new addition to a family of high resolution multi-channel converters.

As demand increases in the highly competitive semiconductor industry for smaller, more functional ICs at lower costs, without any performance or reliability sacrifices, the right packaging can mean the difference between success and failure. Given the global downtown in the semiconductor industry, failure is simply not an option.
The AD5379 is a 40-channel 14bit digital-to-analogue converter (DAC) that provides design engineers with a compact solution for multiple test signals with high accuracy and stability, all in a 13mm square footprint on their printed circuit board.
In producing products such as the AD5379, Analog Devices comes across a number of critical packaging issues:
n Cost per unit.
n Space and weight of the unit.
n The capacity to dissipate power and heat.
n The capacity to handle complex devices with affecting the behaviour of the module.
n Incorporation of multiple chips in a single compact outline.
Despite advances in packaging techniques, finite element analysis remains the bedrock for solving these issues at Analog Devices.
According to Tom Moore, a staff engineer at Analog Devices' design facility in Limerick, Ireland, IC packaging has moved on considerably from the crude slabs of epoxy used when surface mount technology (SMT) was first introduced about 15 years ago.
"Back then, when finite element models were created analysts concentrated on the physical damage to the chip and on elastic stresses causing distortion of the electrical characteristics of the circuits," reports Moore.
He continues, "Now our analysis is concerned with damage to the moulding compound. With miniature packages the moulding compound is about as thick as a playing card and there are potential issues with its mechanical performance due to the differential in coefficients of thermal expansion (CTE) of the compound itself and the two other major materials - silicon and substrate, (either copper or glass-reinforced BT resin."
"While the moulding temperature of 175¼C is a stress free temperature for these materials, when the parts cool to room temperature the substrate and moulding compound shrink considerably more than the silicon. Silicon has a high elastic modulus) and because the compound is extremely thin, it carries a much higher level of stress than the silicon. This is, in fact, a complete reversal of the problem packaging designers first faced with SMT 15 years ago."
Analog Devices' design team has recently migrated towards the use of ball grid array (BGA) devices to house chips because of the high number of I/Os (inputs/outputs). The BGA is attractive because of the high density of connections it makes with the circuit board but, according to Moore, this leads to additional packaging issues because the moulding compound is only applied to the top of the IC, and there is an imbalance in the stress deformation.
Moore continues: "With the moulding compound on top, the silicon in the middle and BT laminate on the base of the IC, there are three different coefficients of thermal expansion which cause significant deformation problems. As the packages become larger to house more functionality, as in the case of the BGA, then the warping increases and the problem is magnified."
Once a product is conceived, the specification arrives with the packaging team to determine the best type of packaging to ensure 'manufacturability' is designed into the chip from the outset. Ease of manufacture, yield and reliability are the three main concerns at this point of the product development process.
A finite element model of the IC assembly is built in ANSYS so that the optimal configuration of the materials can be determined. There are a large number of variables between material properties and possible thicknesses, so multiple iterations have to be run in ANSYS FE to find the best design.
"Finite element analysis greatly reduces the number of physical prototypes that need to be built, which is critical in this time-sensitive marketplace," adds Moore. "However, because there are so many variables we have to run many cycles of analysis. Even with fast workstations this can be a time intensive exercise."

Moore and his team have also used FEA to understand critical problems in the continuing development of multi-chip systems. This has lead the establishment of new design rules for ball grid array (BGA) packaging techniques.
"In the early nineties we used ANSYS FEA to determine that a multi-chip structure containing two integrated circuits was feasible," reports Moore.
"However, with the migration towards ball grid arrays, we tried to upgrade to a three chip BGA; however we encountered solder resist cracking at the edge of the die. This cracking was affecting the copper interconnects on the substrate. We ran ANSYS models of the multi-chip BGAs and discovered that the cracking was due to the shrinkage of the die-attach fillet at the sides of the die. The crack was found to propagate downwards into the copper traces. We found through a long series of ANSYS parametric analyses that with available material sets this was unavoidable. This issue had not been detected before in a single chip BGA because the copper traces did not run across the die-attach fillet in such assemblies." As a result Analog Devices implemented work-around for this problem so that it does not impair the reliability of its multichip BGA products.
Analog Devices continues to use FEA to develop rules for package construction and for the layout of circuitry on chips, such as the orientation and location of thin film resistors.
"In using ANSYS FEA to examine thermal and mechanical stress issues, we are able to confirm our engineering judgment that certain characteristics are the root causes of problems. This has lead to fewer prototypes and greater confidence in the first prototype", says Moore.

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David Barry is with ANSYS Europe, Riseley, Berkshire, UK. www.ansys.com