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Sign-off and verification tools for latest ARM cores on 7nm process

25th August 2017

Posted By Paul Boughton


Cadence Design Systems has optimised its full-flow digital and sign-off tools and verification suite for ARM’s Cortex-A75 and Cortex-A55 processor cores that use the latest DynamIQ technology.

Cadence has also delivered new 7nm-ready Rapid Adoption Kits (RAKs) for the Cortex-A75 and the Cortex-A55 CPUs, which include the DynamIQ Shared Unit (DSU) that provides a shared level three cache between the CPUs, and a 7nm-ready RAK for the Mali-G72 GPU.

Customers are already using the complete digital and sign-off flow and the Cadence Verification Suite to tape out system-on-chip (SoC) designs with the cores.

The RAKs accelerate physical implementation, sign-off, and verification of 7nm designs, allowing designers to deliver mobile and consumer devices to market faster using the scripts, example floorplan and documentation for Arm’s 7nm IP libraries, as well as specialised technical support for ARM IP implementation.

The CadenceRTL-to-GDS flow incorporates several tools in the RAKs, including the Innovus Implementation System that provides statistical on-chip variation (SOCV) propagation and optimisation results in improved timing, power, and area closure for 7nm designs.

It also includes Genus Synthesis for RTL synthesis supports all the latest 7nm advanced-node requirements and provides convergent design closure using Innovus.

The Conformal Logic Equivalence Checking (LEC) tool ensures the accuracy of logic changes and engineering change orders (ECOs) during the implementation flow while the Conformal Low Power tool enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs.

The Tempus Timing Signoff is a key tool for Cadence, providing path-based, sign-off-accurate and physically aware design optimisation, providing the quickest path to tapeout, while the Voltus IC Power Integrity tool provides static and dynamic analysis of the power used during implementation and sign-off ensures optimal power distribution.

“The Cortex-A75 and Cortex-A55 CPUs deliver distributed intelligence from edge-to-cloud, and pairing them with the Mali-G72 GPU enables consumers to experience stunning graphics efficiently across multiple devices,” said Nandan Nayampally, vice president and general manager of the Compute Products Group at ARM. “By continuing to collaborate with Cadence on the delivery of new digital implementation and signoff RAKs along with optimization of the Cadence Verification Suite, our mutual customers can quickly integrate and augment their differentiated solutions for next-generation devices.”

The Cadence Verification Suite that has also been optimised for these ARM cores, with the JasperGold Formal Verification Platform, Xcelium Parallel Logic Simulation tool and Palladium Z1 emulation tool for running ARM models.

“The Protium S1 FPGA-Based Prototyping Platform can be integrated with palladium and DS-5 tool to start software development before the hardware is ready.

“We worked closely with Arm to optimise our advanced digital implementation and sign-off solutions and our verification solutions for the new Arm CPUs and GPU so our customers can efficiently create 7nm mobile and consumer designs,” said Dr Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence.

“Designers using the RAKs and the Cadence Verification Suite can benefit from improved PPA and reduced project times, while creating the most advanced Arm-based products.”









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