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J-Link debug support for SiFive's RISC-V Coreplex IP

29th September 2017

Posted By Paul Boughton


Segger’s J-Link debugger now supports the SiFive Coreplex IP that is based on the open source RISC-V 32bit microprocessor architecture.

RISC-V was born from the need to address the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, as an open source, non-proprietary alternative to ARM and MIPS IP cores.

SiFive was founded by the inventors of RISC-V – Yunsup Lee, Andrew Waterman and Krste Asanovic – to democratise access to custom silicon.

In its first six months of availability, its HiFive software development boards have been delivered to thousands of developers in over 40 countries.

“In order to bring RISC-V and custom silicon to its full potential, the ecosystem needs a full complement of established commercial tools with which to validate designs,” said Jack Kang, vice president of product and business development at SiFive. “Support from Segger’s industry-leading J-Link debug probe family is a huge step for embedded developers who wish to debug software and production program chips using RISC-V cores. We look forward to our continued partnership with Segger and are excited to see how this development impacts the entire RISC-V community.”

All current J-Link models now support debugging of RV32 RISC-V cores. This includes support from Segger’s GDB Server, which is part of the J-Link software package that supports SiFive’s free Eclipse-based Freedom Studio. J-Link’s high performance and functionality allows it to be easily used and it provides reliable, professional support to RISC-V cores.

Features also include a direct Flash memory download via an open flash loader interface giving SiFive and the RISC-V ecosystem access to Segger’s vast catalog of supported flash devices.

For systems running code from flash memory instead of RAM, there is an unlimited number of breakpoints not only in RAM, but also in Flash (with higher end J-Link PLUS, J-Link Ultra + and J-Link PRO models).

“RISC-V is a great CPU architecture. With various open-source and commercial implementations, we believe that it will become very popular, very fast,” said Alex Grüner, J-Link product manager and CTO of Egger. “J-Link’s family of professional debug probes are now available to help contribute to and build on the success of RISC-V.”

Said Rick O’Connor, chairman of the RISC-V Foundation: “The fact that Segger is seeing commercial demand for RISC-V is evidence that open-source semiconductors are enabling a new wave of silicon design. SiFive and others implementing RISC-V cores based on SiFive’s Coreplex IP will now have the necessary tools to simplify their development workflow.”

The low-cost version J-Link EDU allows students and hobbyists to use professional debug technology with RISC-V.

With the J-Link family, investments in the debug probe are preserved when changing compiler or even CPU architecture as it supports multiple CPU families so there is no need to buy a new J-Link or new license when switching to a different yet supported CPU family or toolchain.

All J-Links are fully compatible to each other, so an upgrade from a lower-end model to a higher-end model is a matter of a simple plug-and-play.









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