Cadence Design Systems has updated its Allegro PCB tool to make design cycles shorter and more predictable, writes Nick Flaherty.
Allegro 16.6 includes a new PCB Designer Manufacturing Option, which can shorten the time to create manufacturing documentation by up to 60 percent, and several key technology updates catered to increase efficiency, control and productivity for designers, while streamlining handoff to manufacturing.
It also includes a Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules. The Documentation Editor module can speed up overall fabrication documentation by up to 60%.
Allegro Rules Developer and Checker, which allows users to develop custom fabrication and assembly rules to extend capabilities provided by the PCB Designer and the Manufacturing Option.
This provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB.
Other capabilities include adding return path vias while routing differential pairs, ensuring a ground current return path for differential pair vias, and updates to avoid coupling of high-speed signals to the FR-4 fabric weave, making it easy for designers to create off-angle routes based on user-defined parameters. This can accelerate the PCB layout process significantly.
The tool also allows for adjusting spacing for signals in interfaces such as DDR3 and DDR4, allowing users to compress signals in high-density route areas, and to spread signals to avoid crosstalk between signals or make space for tuning.
A new shape-editing AppMode allows users to create and modify complex shape geometries very easily and quickly for copper shapes, flex cover lay geometries and complex pad shapes.
“The Allegro portfolio release targets critical design goals for PCB designers who are focused on increasing productivity, while operating under tight schedules and increasing complexities,” said Saugat Sen, vice president of R&D, PCB and IC Packaging Group at Cadence. “To make the design process more efficient, Cadence introduced the Allegro Rules Developer and Checker, which provides a relational geometric verification language that enables designers to extend the standard set of rules to ones that are tailored to their needs.”