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12.5 Gbps SerDes Core in 65 Nm CMOS process

21st February 2013


Avago Technologies says it is among the first manufacturers to validate its SerDes core in 65 nm CMOS process technology.

This advances the state of SerDes (Serialisation/Deserialisation) ASIC core design from today's mainstream 90 nm to 65 nm process technology.

Avago's embedded SerDes intellectual property (IP) core offers extremely low jitter, making it possible to integrate as many SerDes channels as needed onto a single 65-nm CMOS (complementary metal oxide semiconductor) chip, each operating at up to 12.5 Gbps. Additionally, the new SerDes core features Avago's proprietary clockless Decision Feedback Equalisation, on-chip BERT for channel bit error rate optimisation, LC-based oscillator for improved power-supply noise rejection, and 1149.6 AC-Extest for testing AC-coupled connections.

This core is the latest in Avago's broad embedded SerDes offering which include cores planned for use in Fibre Channel, XAUI/CEI, XFI, 802.3ap and PCI-Express applications.

For more information, visit www.avagotech.com

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