Architecture reduces the size of array

Paul Boughton

Configurable array processor developer Elixent has developed a new architecture that reduces the size of the array by 40percent for the same performance.

The D-fabrix array of over a thousand 4bit ALUs and associated interconnect switch blocks is aimed at algorithm processing in consumer and mobile applications as part of an SoC, with chip being developed by Toshiba and Panasonic, among others.
Version 2 tackles a key problem that arose from the use of the first generation. There, more than half the ALUs in the array were being used to handle multiplexing of data, rather than data processing which was extremely inefficient.
In version 1.2, Elixent added two multiplexers in the ALU to compensate, but still a quarter of the ALUs were being used as multiplexers. With Version 2 the multiplexers have been separated out into the switch box, and a level of local routing added. This has reduced the length of the wires, reducing the capacitance of the interconnect and so reducing the power consumption or allowing a higher clock rate. Now the routing tools that take the RTL of the algorithm and map it to the array cannot use the ALUs as multiplexers, leaving the ALUs free for calculations. Dedicated logic has been added to handle bit manipulation, taking about 20percent of the load off the ALUs.
In benchmarks on existing designs, the changes benefited algorithms such as a Viterbi filter in a wireless LAN best, with a
4x increase in performance density, which means the same function can be handled in a quarter of the number of ALUs.

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