**During the past 10 years the clock frequencies of CPUs has increased by a factor of almost 100 and correspondingly the frequency spectrum of interference voltages has shifted to a higher level. **

But aslow' electronics can also generate interference voltages in the high frequency range. If they are not suppressed effectively on the board to start with, the costs to achieve EMC compatibility can be considerably higher than the initial measures. But the suppression of high frequency interference voltages requires a fresh approach and the abandonment of old habits.

Often too little importance is attributed to the parasitic elements of the building blocks used for decoupling. The old concept to use alarge' capacitors for low frequencies and asmall' capacitors for high frequencies is therefore not necessarily correct and successful. The parallel switching of different capacitors can be problematic. It is also not sufficient that the capacitors for the higher frequencies are asmall' in value. Other criteria are decisive here.

New generations of computer boards as a rule involve an increase in clock frequency. In the last 10 years the clock rate of CPUs in the IT area has increased by a rate of 50 to 100. The clock rates of other functional modules have to follow suit, if a abottleneck' in the overall performance is to be avoided.

Industry applications do not follow the trend in the desk top areas as quickly, but cannot entirely ignore it due to the availability of silicon. Therefore the spectrum of interference voltages again and again gets pushed to higher frequencies, which cannot be decoupled properly with conventional methods.

It is not only the clock frequency alone that creates problems with EMC. The rise and fall times of the signals and with this the change of the power input of the driving circuits generates interference voltages on the inductive elements of the power supply path. That means aslow' clock rates too can cause the same problems as high speed signals. If the signals are driven by the same silicon, the rise and fall times are the same and the same interference voltages on inductive elements in the power input are generated:

UL = L di/dt (1)

For instance the interferences of the output voltages of a switched power supply were measured. The basis frequency was at 100kHz, today still a typical region for the working frequency of a transducer and really far from high speed. It should not be a problem to suppress this. But the interferences are not in sinus frequency, but they are strong needle peaks. The rise time corresponds to a sinus frequency of 50MHz. For this conventional Elkos are completely overstretched. Even special capacitors for switched power supplies cannot suppress these. And the asmall' ceramic capacitors are not particularly active at 50MHz.

**Parasitic elements**

The parasitic elements, that determine the decoupling of the high frequency area considerably, are the ESR (Equivalent Series Resistance) and the ESL (Equivalent Series Inductance) of the capacitor. In the first the electrical losses that occur in the di-electric during the reloading of the capacitor and the resistance of the leads are combined. The inductance of the leads and the body, which are determined through the internal current loop, are described in the equivalent circuit diagram as ESL (Equivalent Series Inductance). Whilst the ESR is strongly influenced by the characteristics of the di-electric, the ESL is dependent on the geometry only. By geometry we should also understand separated current loops of new constructions, where internal magnetic fields compensate each other and thereby reduce the inductance of the capacitor.

Looking at the equivalent circuit diagram makes it immediately clear, that this kind of assembly has its own resonance frequency fr, in particular, when the imaginary parts of the impedance ZC offset each other:

ZC = ESR +j(wL - 1/(wC)) (2) l = 1/aC (3) r = 1/(2¼ sqr(LC) (4)

With frequencies below the resonance the device acts like a capacitor, above its self resonant frequency it transforms into an inductance. With conventional ceramic capacitors used for decoupling, the self resonance lies between 1MHz and about 10MHz.

This is clearly well below 50MHz, the value for a frequency of interference voltages generated by a typical dc/dc convertor so from the decoupling side one should differentiate between high speed and atraditional'. All interference with a spectrum that lie above the self resonance of capacitors used are high speed or high frequency with regard to the decoupling. With this the harmless convertor now becomes a high speed element and measures to deal with interference have to be chosen with high speed in mind.

If only the formula of the self resonance is taken into account, the suggestion to push the effectiveness of the decoupling capacitors to higher frequencies and thereby choosing lower capacity values, seems a logical one. Looking at the resonance frequency this seems plausible and corresponding recommendations are known. However, looking at the total process characteristics of the impedance over the frequency it soon becomes clear: with this method we only loose effectiveness (Fig.2). The recommendation has to be: For the component size or geometry, that determines the ESL, the largest available and economically acceptable capacity has to be chosen.

The sacrifice of capacity does not improve the effectiveness in the area of higher frequencies (>a10MHz), the impedance is not lower through this! Below the resonant frequency, in the capacitive area, the impedance is higher on account of the lower capacity, therefore effectiveness is given away (Fig.3).

**Selection criteria**

Of course there are specific constructions with especially low ESL, such as capacitors from AVX, Murata and in the meantime also other manufacturers, that have the leads on the long side (Type 0612,0508). aFeed through capacitors' in a 4-pol design (AVX, Murata, Syfer etc), that are not really meant for decoupling, are very suitable through their markedly small ESL of lower than 1nH. From the pricing side the simple 0603 version, which can reach 0,7nH, cannot be undercut. In contrast to the above mentioned specific types these are available in acheap' Y5V ceramics and have considerably higher capacity values (1 µF,Tayo Yuden). aCheap' in this case means: not only economically favourable, but technically advantageous in particular.

**An end to old customs **

The revelation probably takes a little time to get used to, but we decouple in high frequency areas (>10MHz) with inductances. The capacity gained is only an additional bonus for the current blocking. Following this train of thought, decoupling capacitors have to be chosen by their parasitic elements ESR and in particular ESL. And both values should be as low as possible. Unfortunately these values are very seldom mentioned on data sheets. The only thing to do is to contact the supplier or manufacturer. Sometimes even SPICE models or

S- parameters are obtainable, which prove extremely helpful in simulations.

This means the temperature coefficient of the capacitor (the capacity) is not a deciding factor -- the ESL is a pure question of geometry and current loop in the capacitor.

So which role does the ESR play? If the diagram of the impedance characteristic over the frequency is pictured, one could come to the conclusion, that the ESR too should be as low as possible. However, as several different capacitors are wired in a parallel, which is the rule in most cases, parallel resonance circuits are created. These cannot be avoided, in an extreme case resonance circuits are only created on one capacitor and the inner layer capacitance of the printed circuit board. And as nobody, who uses fast logic circuits, can go without power distribution on planes within the PCB, they will have to live with the aSword of Damocles' of parallel resonances.

**Serial resonances**

Both capacitors, or groups of two different capacitors, will have different serial resonance frequencies as either the capacitance, or the ESL (different construction, type etc.) will differ. In the area below the deeper resonance frequency, both capacitors will still be effective as capacitors.

But in the area above the resonance frequency both capacitors only appear as inductance, wL is larger than 1/wC in each case.

In the frequency area between these two resonance frequencies one of the capacitors is capacitatively active and the other inductively and both create a parallel resonance circuit.

Parallel resonance circuits show considerably higher impedance with the presence of resonance than the impedance of each individual path on its own. In practice this means that in this frequency area the decoupling is considerably worse -- and can be almost non existent -- and interferences can spread themselves unhindered onto the board.

In the laboratory, a power supply with the occurrence of (parallel) resonance switched off from the +5V rail. The (VME-) backplane was clocked via an I/O-Board with the corresponding frequency (Fig.4). In practice this could have dramatic consequences. You control a machine or process and through signals from this process, that happen to meet this parallel resonance, the control can be turned of abruptly or the equipment can loose control.

The ESR should therefore be low, possibly considerably under 10mOhm, but not too low, in order to suppress the resonance sufficiently. A simulation of the module circuit in relation to parallel resonances or at least a test before it release is highly recommended. It is of course also useful to make sure that the self resonances of the capacitors used are not far apart on the frequency scale.

**Dispense with old customs**

Choosing decoupling capacitors by their parasitic elements ESR and ESL, which unfortunately never appear in a data sheet, we would like to address a further aspect. If it was possible for find capacitors with an ESL under 1nH at acceptable costs, these are soldered on to SMD pads, which are connected over a long trace to a via. What the designer does here is equal to someone taking the gears two to six out of a sports car. The inductance of a capacitor (ESL) has to be calculated with the inductance of the entire interference suppression circuits, in which currents flow, in mind. Through layouts that have not been adapted a large part of the performance is lost and it is not particularly sensible to discuss a further reduction of the ESL, which in contrast to the package 0603 can still be achieved with special constructions (AVX, Murata, Syfer).

**Conclusion**

It is not so much the frequency, but the edges and peaks of the signals which determine the interference spectrum. In this way even supposedly slow switching can send out considerable interferences. This interference spectrum as a rule reaches far into the frequency area, which lies above the resonance frequency of common capacitors. The suppression characteristics of the capacitor is only determined here through its inductance.

As this is not temperature dependent and the temperature coefficient of the dielectric does not play a part, the type of the ceramic (Z5U, X7R, etc) can be chosen to the ESR, the Equivalent Series Resistance. It has to be taken into consideration, an ESR which is too low, eg that has already been achieved with X7R ceramics, is not sufficient any more to suppress ringing for parallel resonance circuits effectively. In the end the layout has to be arranged with the lowest possible inductance of the suppression circuit of the whole loop.

Suppression of high frequency interferences as near as possible to the source is an effective and economical measure in order to avoid later problems with the EMC of the building element or system.

aCorrectly' chosen capacitors are not necessarily dearer than others and a good layout in the series does not cost anything in comparison to expensive filters, when the film is copied onto the copper.

Andreas Lenkisch is Product Manager for Backplanes at Schroff, Germany. " target="_blank">www.schroff.de

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