The non-volatile memory market is changing dramatically, and the 300mm SP1 fab at Aizu Wakamatsu, Japan, is a key part of the Spansion strategy. As Intel and STMicroelectronics combine their non volatile memory businesses into a potentially market leading company, capacity is the key to producing the right products at the right cost, and SP1 is a major step forward for Spansion.

The fabrication plant at Aizu Wakamatsu already houses a 200mm fab set up with the merger of the memory businesses of Fujitsu and AMD (FASL) that founded Spansion. This provides the infrastructure for SP1, but there have been some dramatic changes that allow SP1 to be set up to handle 300mm wafers with lithography down to 45nm. There is also a dramatic increase in flexibility in placing equipment which will have a significant impact on the efficiency and throughput of the fab.

“This is the very first 300mm NOR flash plant in the world,” said Masao Taguchi, president of Spansion Japan. “The investment in total for phase one is $1.2bn.”

NOR flash is used in mobile phones for data and programme storage, rather than the NAND flash technology used in mass storage such as MP3 players.

“Going forward it is important to design a factory for the latest technology and that’s what we are doing with SP!” said Bertrand Cambou, president and chief executive officer. “We are currently investing in two paths – first is to use a silicon foundry one node behind (TSMC) in order to dedicate our cash to the latest technology. SP1 has been designed with 45nm and 32nm in mind even though today we are running 65nm.”

The key is that the economics of the industry are changing and there are also significant shifts in the technology

Spansion has been pioneering its MirrorBit technology which instead of a floating gate uses stored charge (like a capacitor) which is easier and easier to make and more scalable.

“If you look at mobile phones the NOR flash technology is fast enough to work with the applications processor and baseband processor and we this our technology will get a significant cost reduction,” said Cambou. “There is a partial replacement possible as it will reduce the power consumption and can be used for instant reboot as it keeps data in the core. By the fourth quarter of 2007 all our Mirrorbit was in SP1 and that means the entire family will be produced on 300mm wafers.”

This gives a huge economic advantage.

“Past 90nm the cost per gigabit is below that of DRAM and the first node where that will be significant is 65nm,” he said. “Floating gate technology is running out of steam in both NOR and NAND and there is a transition issue between floating gate and other technologies for other companies. I believe SP1 will drive use all the way to the 20nm node.”

The process technology for SP1 has been developed at the Submicron Development Centre (SDC) in San Jose, California, that was acquired from AMD and copied exactly to the fab. This is combined with the fab management skills from Fujitsu to optimise the layout and operation of the fab alongside the process.

“Soon it will be impossible to scale floating gate technology,” said Jim Duran, executive vice president of operations and chief operating officer at the plant. “We believe fundamentally its more scalable, simple and less expensive to build and we are investing all our resources into that. 45nm is already running full flow silicon at the SDC and we have been feasibility work on the nodes beyond that.”

“In this business you have to be the low cost producer, and the keys to being the lowest cost are leading edge technology, and you have to be a leader in test technology. All the 65nm products include built in self test (BIST) allowing us to test a wafer at a time rather than die by die, and this dramatically reduces the cost.

The fab has implemented an overhead carrier system for 300mm wafers which is a significant weight increase over 200mm. The conveyors run for 2.7km throughout the fab, dropping down to the equipment which is all sealed. This means the ballroom of the fab can be class 100 rather than having to have the equipment in sealed class1 areas which is the case for the existing 200mm fab and this limits where equipment can be placed. Instead, this combination of sealed equipment and the flexible conveyor system allows equipment to be placed anywhere, and this allows Spansion to optimise the equipment flow and squeeze more equipment into the fab, making it the manufacturing cost effective.

The conveyor also helps keep the diffusion parts of the process separate from the copper parts, and all the copper activity is kept in a totally separate area and even the staff where different coloured ‘bunny suits’ in that area to ensure there is no cross contamination.

While the capacity is initially low at 2000 wafers a month, there is a worry that there isn't enough capacity to make a difference.

“For me this is a mega-fab,” says Duran. “Bigger is better but only up to a point. Once you get these fabs up to 4000 to 7000 wafers a week we are on the flat part of the yield curve and after that there is only incremental investment needed.”

The next stage is to facilitise the second half of the fab, but that will depend on economic conditions say Cambou and Doran.

But SP1 marks Spansion’s move into true high volume manufacturing, supplying a key component for next generation equipment with a scalable, cost effective technology. The fab provides the other side of the equations to make the chips in 65nm, 45nm and even 32nm process technology well into the future.

MirrorBit technology

MirrorBit is fundamentally different and more advanced than conventional multi-level cell (MLC) and single-level cell (SLC) floating gate technology.

The MirrorBit cell doubles the intrinsic density of a Flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell serves as a binary unit of data (eg either 1 or 0) that is mapped directly to the memory array.

Reading or programming one side of a memory cell occurs independently of whatever data is stored on the opposite side of the cell. As a result, MirrorBit technology delivers higher read and write performance for wireless and embedded markets.

The array design also greatly simplifies a device's topography and manufacturing process to make the devices more cost effective. Applications include:

• Mobile phones and cellular handsets
• Smartphones and PDAs.
• Set-top boxes and DVRs.
• DVD players and recorders.
• Networking and telecom equipment.
• Printers and peripherals.
• Automotive navigation.
• Gaming systems.
• Industrial & embedded applications.

Building a new 300mm wafer fab for 45nm profcess typically costs $2 to $3bn, which his a huge undertaking for any company. Spansion has done it with $1.2bn, mainly by using the existing infrastructure and spreading the investment out over time.

SP1 at Aizu Wakamatsu has been designed to support up to 4000 wafer starts per week on 300mm wafers, making it a medium sized fab.

“We are investing about half the total to provide 500 wafer a week at SP1,” says Bertand Cambou, president and CEO of Spansion, “because until we need the volume we don’t want to put too much cash into out factories. Moving to the full 4000 wafers a week is going to be set as the business conditions require.”

Spansion in China

Spansion will transfer its 65nm MirrorBit technology to Chinese foundry SMIC to build on 300mm wafers in China. SMIC and Spansion have also signed a preliminary memorandum of understanding which would allow SMIC to enter selected segments of the Flash memory market with a license to manufacture and sell 90nm and 65nm and potentially future Spansion MirrorBit Quad products for the delivery of content such as audio and video on flash devices such as memory cards for the Chinese market.

Spansion has been investing in China for over 10 years and is now a leading Flash memory provider to the top consumer electronics and wireless OEMs in the region. The investment started with the establishment by AMD, Spansion’s former parent company, of a final manufacturing facility in Suzhou that is now one of the world's largest producers of memory Multi-chip Packages (MCPs). Since then, Spansion has added local design centres in Suzhou and Beijing, and sales and marketing offices in Beijing, Shanghai and Shenzhen.

Through the foundry agreement with SMIC, Spansion will have wafer manufacturing capabilities in China for the first time.