Consumer markets demand more cheap, easy to use and portable applications. This, together with the manufacturing technology trend, pushes the semiconductor industry to higher levels of integration.

This has already happened for digital applications, now combining data processing – games, voice, music, video, etc – with memory, encryption and copyright protection capabilities on single silicon chips with hundreds of millions of gates. This is quite an achievement which required significant innovations in EDA software, such as functional verification, signal integrity analysis, timing closure and design for manufacturing.

Nevertheless, there is a greater challenge yet to be addressed – allowing those huge digital chips to communicate wirelessly. Today, most consumer market devices feature wireless communication, but up until now this has been implemented with separate dies, which translates into larger equipment with shorter battery life and potentially higher cost.

Actually the latter is not true because the integration of RF blocks for wireless communication on the same die as digital processing causes a longer time to mass production that is incompatible with the short product life cycle of consumer equipment as well as a dramatic drop in yield.

Of course, yield tends to decrease when integrating two die into one, but the very poor yield of devices combining digital and RF is mostly a result of design errors and, more specifically, electrical signal integrity (ESI) issues. Increasingly ESI represents a major challenge to designers, causing lengthy design cycles and forcing extra prototype manufacturing.

Electrical signal integrity

Switching activity produced by high speed digital processing as well as high frequency and/or high power analogue signals all threaten ESI in two main ways: semiconductor carriers are released in the substrate through the bulk of the devices; and large and fast current consumption by the power supply grids produces significant variations in the potential. This electrical fluctuation spreads through the entire integrated system through a combination of coupling of the substrate, interconnects and package, and these various cross talk mechanisms act as a passive filter that propagates noise directly to sensitive victim circuits (Fig.1).

When reaching victim cells, coupling noise produces performance losses such as signal delays, bandwidth decrease, phase noise and signal-to-noise decreases, that lead to system dysfunction (Fig.2) this has to be tackled throughout the design cycle.

Floorplanning is critical to permit early assessment of ESI. A key factor is that floorplanning itself is not a monolithic job, and the level of design detail might vary dramatically whether it is estimated before the logical synthesis stage or before physical place-and-route. Right after RTL synthesis, physical information is extremely scarce and can be as limited as estimated block sizes and gate counts.

As a result, system integrators receive very limited information regarding critical ESI metrics and design guidelines and the communication hole between block authors and system integrators imposes a trial and error methodology, leading to significant over-engineering, re-spins and poor yields.

A comprehensive solution to ESI in mixed signal SoCs involves two complementary requirements. Firstly, various extraction and analysis tools are necessary to help all engineers in the design chain. Secondly, the tools must be designed to enforce an easy and robust communication between digital, analogue and RF designers.

The WaveIntegrity software platform (Fig.3) is built around a common set of extraction and analysis algorithms and integrates into the design flow to help RF designers analyse their circuits to maximise immunity to cross-talk as well as allow final IP sign off to capture the circuit sensitivity metrics that are needed during system level integration.

Digital designers also have the ability to quantify cross-talk noise generated by the digital circuits, whether a simple library standard cell or complex IP block such as a complete microprocessor.

At the system level, the tool lets integrators analyse and solve ESI issues from early floorplanning down to sign-off verification of the physical design.

There are two ways of using the tool by analogue and RF designers.

During interactive IP design, WaveIntegrity helps the designer understand and maximise the performance of the circuit by maximising the immunity to cross-talk noise. This identifies aggressor circuits and victims and how they demonstrates how they interact so that changes can be made in either and avoid the lengthy cycles of change and analysis that comes from using point tools.

The second approach is during IP sign-off, to automatically extensively test the signal integrity and generate a macro model that can be used later in the system assembly stage.

Digital designers can use the tool to automatically generate macro models of the aggression of the digital circuits along with the noise sources in both the time and frequency domains, together with local substrate and interconnect parasitics. This includes several statistical noise models, with worst case, typical and least noise injected by each IP block. This is critical to allow integrators to better assess the eventual design margin of the full system.

Floorplanning

During floorplanning it is possible to assess and solve ESI issues very early in the design cycle. With WaveIntegrity, the algorithms used to extract and analyse the ESI are common throughout all levels of details, and that opens up innovative design methodologies and a natural convergence to more accurate design descriptions.

After RTL synthesis, an estimation of IP placement and the power grid are provided by the designer to extract noise cross talk from a combination of substrate, interconnect and package. A dedicated algorithm uses the aggression models from the standard cell library to estimate the worst- typical- and best-case models for each synthesised block. This makes it possible to compute a first estimation of cross-talk noise distribution and assess system feasibility by comparing the noise at each victim circuit with the thresholds captured by the authors of the victim IP blocks.

Later on after physical synthesis, IP block descriptions are implemented and more accurate aggression models can be calculated. Then the cross talk noise is re-analysed to provide a more accurate assessment.

When the assessment is marginal, the analysis report system can be used to identify the major sources of interference for each vitctim as well as to follow the path through the combination of substrate and interconnect. This dramatically improves the efficiency of designers in increasing the robustness of the ESI performance.

Final verification

The last application allows final assessment of ESI based on the actual physical system implementation stored in the physical design database. The greater level of detail available at this point allows for more accurate modelling of the aggression and cross-talk functions.

Nevertheless, this does not impact significantly on the overall assessment of the performance as the analysis uses the floorplanning results to focus the accuracy along the critical paths that have already been identified.

Conclusion

A consistent set of algorithms for analysing ESI throughout the design cycle provides the designer with some key advantages. Being able to identify and measure the effect of both aggressor circuits and the vulnerability of the victim circuits automatically from both analogue and RF blocks and other digital blocks across the chip is vital. Using this data early on for floorplanning, though the design phase and in physical verification provides a consistent, measurable, analysis methodology, rather than using point tools to identify problems and them trying to solve the problems without introducing more problems in other areas.

In this way the design times of integrated RF devices can be decreased, yields increased and costs improved to add wireless capabilities cost effectively to the next generation of consumer products.u

Francoise Clement is chief technology officer and co-founder of Coupling Wave Solutions in Grenoble, France. Coupling Wave solutions was founded in Grenable, France, in August 2004 by Breuc Turluche, the former president of Ansoft Europe and Francois Clement, co-founder of EDA startup Snaketech. Both have more than 15 years experience in the EDA industry, and Clement holds several patents.